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preliminary data sheet july 2001 orca ? ort82g5 1.0?1.25/2.0?2.5/3.125 gbits/s backplane interface fpsc introduction agere systems inc. has developed a next generation fpsc intended for high-speed serial backplane data transmission. built on the series 4 reconfigurable embedded system-on-chips (soc) architecture, the ort82g5 is made up of backplane transceivers con- taining eight channels, each operating at up to 3.125 gbits/s (2.5 gbits/s data rate), with a full- duplex synchronous interface with built-in clock and data recovery (cdr), along with up to 400k usable fpga system gates. the cdr circuitry is a macro- cell available from agere's smart silicon macro library, and has already been implemented in numer- ous applications including asics, standard products, and fpscs to create interfaces for sonet/sdh, sts-48/stm-16, sts-192/stm-64, and 10 gbit ethernet applications. with the addition of protocol and access logic such as protocol-independent fram- ers, asynchronous transfer mode (atm) framers, packet-over-sonet (pos) interfaces, and framers for hdlc for internet protocol (ip), designers can build a configurable interface retaining proven back- plane driver/receiver technology. designers can also use the device to drive high-speed data transfer across buses within a system that are not sonet/ sdh based. for example, designers can build a 20 gbits/s bridge for 10 gbits/s ethernet; the high- speed serdes interfaces can comprise two xaui interfaces with configurable back-end interfaces such as xgmii or pos-phy4. the ort82g5 can also be used to provide a full 10 gbits/s backplane data con- nection with protection between a line card and switch fabric. the ort82g5 offers a clockless high-speed inter- face for interdevice communication on a board or across a backplane. the built-in clock recovery of the ort82g5 allows for higher system performance, easier-to-design clock domains in a multiboard sys- tem, and fewer signals on the backplane. network designers will benefit from the backplane transceiver as a network termination device.the first version of the device supports 8b/10b encoding/decoding and link state machines for ethernet, fibre-channel, and infiniband ?. version ii adds sonet data scram- bling/descrambling, streamlined sonet framing, transport overhead handling, plus the programmable logic to terminate the network into proprietary sys- tems. for non-sonet applications, all sonet func- tionality is hidden from the user and no prior networking knowledge is required. version ii adds decimation and interpolation for con- nections at 622 mbits/s rates. table 1. orca ort82g5 family?available fpga logic ? the embedded core and interface are not included in the above gate counts. the usable gate counts range from a logic-only gate count to a gate count assuming that 20% of the pfus/slics are being used as rams. the logic-only gate count includes each pfu/slic (counted as 108 gates/pfu), including 12 gates per lut/ff pair (eight per pfu), and 12 gates per slic/ff pair (one per pfu). ea ch of the four pio groups are counted as 16 gates (three ffs, fast-capture latch, output logic, clk, and i/o buffers). pfus used as r am are counted at four gates per bit, with each pfu capable of implementing a 32 x 4 ram (or 512 gates) per pfu. embedded block ram (ebr) is counted as four gates per bit plus each block has an additional 25k gates. 7k gates are used for each pll and 50k gate s for the embedded system bus and microprocessor interface logic. both the ebr and plls are conservatively utilized in the gate count cal cula- tions. ? 372 user i/os out of a total of 432 user i/os are bonded in the 680 pbgam package. device pfu rows pfu columns total pfus user i/o luts ebr blocks ebr bits (k) usable ? gates (k) ort82g5 36 36 1296 372/432 ? 10,368 12 111 380?800
table of contents contents page contents page 2 agere systems inc. preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel introduction..................................................................1 embedded function features .....................................4 intellectual property features......................................4 programmable features..............................................5 programmable logic system features .......................6 description...................................................................7 what is an fpsc? ....................................................7 fpsc overview .........................................................7 fpsc gate counting ................................................7 fpga/embedded core interface ..............................7 orca foundry 2000 development system .............7 fpsc design kit .......................................................8 fpga logic overview ...............................................8 plc logic ..................................................................8 programmable i/o .....................................................9 routing ......................................................................9 system-level features..............................................10 microprocessor interface .........................................10 system bus .............................................................10 phase-locked loops ..............................................10 embedded block ram ............................................10 configuration ...........................................................11 additional information .............................................11 ort82g5 overview ..................................................11 device layout .........................................................11 backplane transceiver interface .............................11 ort82g5 overview (continued) ...............................12 serializer and deserializer (serdes) ....................14 mux/demux block .................................................14 multichannel alignment fifos ................................14 xaui or fibre-channel link state machine ............14 dual port rams ......................................................14 fpga interface .......................................................15 fpsc configuration ................................................15 backplane transceiver core detailed description ....15 serdes .................................................................15 serdes transmit path (fpga ? backplane) ......18 transmit preemphasis and amplitude control ........19 serdes receive path (backplane ? fpga) .......19 8b/10b encoding/decoding .....................................21 serdes transmit and receive plls ................... 21 reference clock ..................................................... 21 byte alignment ....................................................... 22 link state machines ............................................... 22 xaui link synchronization function ...................... 23 mux/demux block ................................................ 25 multichannel alignment (backplane ? fpga) ....... 27 alignment sequence .............................................. 29 loopback modes .................................................... 32 high-speed serial loopback .................................. 32 parallel loopback at the serdes boundary ......... 33 parallel loopback at mux/demux boundary excluding serdes ............................................... 33 asb memory blocks ............................................... 34 memory map............................................................. 36 definition of register types ................................... 36 absolute maximum ratings...................................... 54 recommended operating conditions ...................... 54 hsi electrical and timing characteristics ................ 54 pin information ......................................................... 57 power supplies for ort82g5 ................................ 63 recommended power supply connections ........... 64 recommended power supply filtering scheme .... 64 package pinouts .................................................... 69 pin information ......................................................... 70 package thermal characteristics summary.................................................................. 87 ja ......................................................................... 87 jc ........................................................................ 87 jc ........................................................................ 87 jb ........................................................................ 87 fpsc maximum junction temperature ................. 87 package thermal characteristics............................. 88 package coplanarity ................................................ 88 package parasitics ................................................... 88 package outline diagrams....................................... 89 terms and definitions ............................................ 89 680-pin pbgam ..................................................... 90 hardware ordering information ................................ 91 software ordering information ................................. 91
agere systems inc. 3 preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel table of contents list of figures page list of tables page figure 1. ort82g5 block diagram ..........................12 figure 2. internal high-level diagram of ort82g5 transceiver ..............................................................13 figure 3. serdes functional block diagram for one channel ...........................................................17 figure 4. ort82g5 transmit path for a single serdes channel ...................................................18 figure 5. ort82g5 receive path for a single serdes channel ...................................................20 figure 6. fibre-channel link state machine state diagram ...................................................................22 figure 7. xaui link synchronization state diagram ...................................................................24 figure 8. transmit mux block for a single serdes channel ...................................................................25 figure 9. receive demux block for a single serdes channel ...................................................26 figure 10. interconnect of streams for fifo ............27 figure 11. example of serdes a alignment and ...27 figure 12. example of serdes a and b alignment ................................................................27 figure 13. example of multiple twin channel ..........27 figure 14. multichannel alignment fifo block for a single serdes channel .....................................28 figure 15. de-skew lanes by aligning /a/ columns ..................................................................30 figure 16. block diagram of memory block .............34 figure 17. minimum timing specs for memory blocks-write cycle ..................................................35 figure 18. minimum timing specs for memory blocks-read cycle ..................................................35 figure 19. receive data eye-diagram template (differential) .............................................................55 figure 20. power supply filtering ............................65 figure 21. package parasitics ..................................88 table 1. orca ort82g5 family ? available fpga logic ...............................................................1 table 2. preemphasis settings ...................................19 table 3. transmit pll clock and data rates ............21 table 4. receive pll clock and data rates .............21 table 5. xaui link synchronization state diagram notation ? variables ..................................23 table 6. xaui link synchronization state diagram ? functions ................................................23 table 7. multichannel alignment modes .....................29 table 8. definition of bits of mrwdxy[39:0] ...............31 table 9. high-speed serial loopback configuration .32 table 10. parallel loopback configuration .................33 table 11. structural register elements ......................36 table 12. memory map ...............................................37 table 13. absolute maximum ratings ........................54 table 14. recommended operating conditions ........54 table 15. absolute maximum ratings ........................54 table 16. recommended operating conditions ........54 table 17. receiver specifications ..............................55 table 18. reference clock specifications (refinp and refinn) ............................................56 table 19. channel output jitter (1.25 gbits/s) ...........56 table 20. channel output jitter (2.5 gbits/s) .............56 table 21. serial output timing levels (cml i/o) .......56 table 22. serial input timing and levels (cml i/o) ...56 table 23. fpga common-function pin description ..57 table 24. fpsc function pin description ..................60 table 25. power supply pin groupings ......................63 table 26. embedded core/fpga interface signal description ...................................................66 table 27. ort82g5 680-pin pbgam pinout .............70 table 28. orca ort82g5 plastic package thermal guidelines .................................................88 table 29. orca ort82g5 package parasitics ........88 table 30. device type options ..................................91 table 31. temperature options ..................................91 table 32. package type options ...............................91 table 33. orca fpsc package matrix (speed grades) .......................................................91
4 4 agere systems inc. preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel embedded function features high-speed serdes programmable serial data rates of 622 mbits/s (sonet only), 1.25 gbits/s, 2.5 gbits/s, and 3.125 gbits/s. asynchronous operation per receive channel with the receiver frequency tolerance based on one reference clock per quad channels (separate pll per channel). ability to select full-rate or half-rate operation per tx or rx channel by setting the appropriate control reg- isters. transmit preemphasis (programmable) for improved receive data eye opening. receiver energy detector to determine if a link is active. 32-bit (sonet or 8b/10b) or 40-bit (raw data) paral- lel internal bus for data processing in fpga logic. provides a 10 gbits/s backplane interface to switch fabric with protection. also supports port cards at 622 mbits/s or 2.5 gbits/s. 3.125 gbits/s serdes compliant with xaui serial data specification for 10 gbit ethernet applications with protection. most xaui features for 10 gbit ethernet are embed- ded including the required link state machine. compliant to fibre-channel physical layer specifica- tion. allows wide range of applications for sonet net- work termination, as well as generic data moving for high-speed backplane data transfer. no knowledge of sonet/sdh needed in generic applications. simply supply data, a 100 mhz ? 156.25 mhz reference clock, and, optionally, a frame pulse. high-speed interface (hsi) function for clock/data recovery serial backplane data transfer without exter- nal clocks. eight-channel hsi function provides 2.5 gbits/s serial user data interface per channel for a total chip bandwidth of 20 gbits/s (full duplex). serdes has low-power cml buffers. support for 1.5 v/1.8 v i/os. programmable sts-12 or sts-48 framing in sonet mode per channel (in version ii). oc-192 framing in quad oc-48 (four channels) also supported. powerdown option of serdes hsi receiver on a per-channel basis. selectable 8b/10b coder/decoder or sonet scram- bler/descrambler (added for version 2). serdes hsi automatically recovers from loss-of- clock once its reference clock returns to normal oper- ating state. in-band management and configuration through transport overhead extraction/insertion in sonet mode (version ii). supports transparent mode where the only insertion is a1/a2 framing bytes in sonet mode (version ii). built-in boundary scan ( ieee ? 1149.1 and 1149.2 jtag) for the programmable i/os, not including the serdes interface. fifos align incoming data across all eight channels (all eight channels, two groups of four channels, or four groups of two channels). alignment is done using comma characters or /a/ in 8b/10b mode or frame pulse in sonet mode (version ii). optional ability to bypass alignment fifos for asynchronous operation between channels. (each channel includes its own clock and frame pulse or comma detect.) frame alignment across multiple ort82g5 devices for work/protect switching at sts-768/stm256 and above rates in sonet mode. addition of two 4k x 36 dual-port rams with access to the programmable logic. intellectual property features programmable logic provides a variety of yet-to-be standardized interface functions, including the following agere me ip core functions: 10 gbits/s ethernet as defined by ieee 802.3ae: ? xgmii for interfacing to 10 gbits/s ethernet macs. xgmii is a 156 mhz double data rate par- allel short reach (typically less than 2") intercon- nect interface. ? x 58 + x 39 + x 1 scrambler/descrambler for 10 gbits/s ethernet. ? 64b/66b encoders/decoders for 10 gbits/s ether- net. ? xaui to xgmii translator, including dual xaui pro- tection. pos-phy4 interface for 10 gbits/s sonet/sdh and otn systems and some 10 gbits/s ethernet systems to allow easy integration of infiniband , fibre-channel, and 10 gbits/s ethernet in data over fibre applica- tions. ethernet mac functions at 10/100 mbits/s, 1 gbits/s, and 10 gbits/s. other functions such as fibre-channel and infiniband link layer ip cores are also going to be developed.
agere systems inc. 5 preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel programmable features high-performance programmable logic: ? 0.13 m 7-level metal technology. ? internal performance of >250 mhz. ? over 400k usable system gates. ? meets multiple i/o interface standards. ? 1.5 v operation (30% less power than 1.8 v oper- ation) translates to greater performance. traditional i/o selections: ? lvttl and lvcmos (3.3 v, 2.5 v, and 1.8 v) i/os. ? per pin-selectable i/o clamping diodes provide 3.3 v pci compliance. ? individually programmable drive capability: 24 ma sink/12 ma source, 12 ma sink/6 ma source, or 6 ma sink/3 ma source. ? two slew rates supported (fast and slew-limited). ? fast-capture input latch and input flip-flop (ff)/latch for reduced input setup time and zero hold time. ? fast open-drain drive capability. ? capability to register 3-state enable signal. ? off-chip clock drive capability. ? two-input function generator in output path. new programmable high-speed i/o: ? single-ended: gtl, gtl+, pecl, sstl3/2 (class i and ii), hstl (class i, iii, iv), zbt, and ddr. ? double-ended: lvds, bused-lvds, and lvpecl. programmable, parallel termination (100 ? ) is also supported for these i/os. ? customer defined: ability to substitute arbitrary standard cell i/o to meet fast-moving standards. new capability to (de)multiplex i/o signals: ? new ddr on both input and output at rates up to 311 mhz (622 mhz effective rate). ? new 2x and 4x downlink and uplink capability per i/o (i.e., 50 mhz internal to 200 mhz i/o). enhanced twin-quad programmable function unit (pfu): ? eight 16-bit look-up tables (luts) per pfu. ? nine user registers per pfu, one following each lut, and organized to allow two nibbles to act independently, plus one extra for arithmetic opera- tions. ? new register control in each pfu has two inde- pendent programmable clocks, clock enables, local set/reset, and data selects. ? new lut structure allows flexible combinations of lut4, lut5, new lut6, 4 1 mux, new 8 1 mux, and ripple mode arithmetic functions in the same pfu. ? 32 x 4 ram per pfu, configurable as single- or dual-port. create large, fast ram/rom blocks (128 x 8 in only eight pfus) using the slic decoders as bank drivers. ? soft-wired luts (swl) allow fast cascading of up to three levels of lut logic in a single pfu through fast internal routing which reduces rout- ing congestion and improves speed. ? flexible fast access to pfu inputs from routing. ? fast-carry logic and routing to all four adjacent pfus for nibble-wide, byte-wide, or longer arith- metic functions, with the option to register the pfu carry-out. abundant high-speed buffered and nonbuffered rout- ing resources provide 2x average speed improve- ments over previous architectures. hierarchical routing optimized for both local and glo- bal routing with dedicated routing resources. this results in faster routing times with predictable and efficient performance. slic provides eight 3-statable buffers, up to a 10-bit decoder, and pa l ? -like and-or-invert (aoi) in each programmable logic cell. new 200 mhz embedded quad-port ram blocks, 2 read ports, 2 write ports, and 2 sets of byte lane enables. each embedded ram block can be config- ured as: ? 1 ? 512 x 18 (quad-port, two read/two write) with optional built in arbitration. ? 1 ? 256 x 36 (dual-port, one read/one write). ? 1 ? 1k x 9 (dual-port, one read/one write). ? 2 ? 512 x 9 (dual-port, one read/one write for each). ? 2 rams with arbitrary number of words whose sum is 512 or less by 18 (dual-port, one read/one write). ? supports joining of ram blocks. ? two 16 x 8-bit content addressable memory (cam) support. ? fifo 512 x 18, 256 x 36, 1k x 9, or dual 512 x 9. ? constant multiply (8 x 16 or 16 x 8). ? dual variable multiply (8 x 8). embedded 32-bit internal system bus plus 4-bit par- ity interconnects fpga logic, microprocessor inter- face (mpi), embedded ram blocks, and embedded standard cell blocks with 66 mhz bus performance. included are built-in system registers that act as the control and status center for the device.
6 6 agere systems inc. preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel programmable features (continued) built-in testability: ? full boundary scan ( ieee 1149.1 and draft 1149.2 jtag). ? programming and readback through boundary scan port compliant to ieee draft 1532:d1.7. ? ts_all testability function to 3-state all i/o pins. ? new temperature-sensing diode. improved built-in clock management with program- mable phase-locked loops (pplls) provide optimum clock modification and conditioning for phase, fre- quency, and duty cycle from 20 mhz up to 420 mhz. new cycle stealing capability allows a typical 15% to 40% internal speed improvement after final place and route. this feature also enables compliance with many setup/hold and clock to out i/o specifications and may provide reduced ground bounce for output buses by allowing flexible delays of switching output buffers. programmable logic system features pci local bus compliant for fpga i/os. improved powerpc ? 860 and powerpc ii high- speed synchronous microprocessor interface can be used for configuration, readback, device control, and device status, as well as for a general-purpose inter- face to the fpga logic, rams, and embedded stan- dard cell blocks. glueless interface to synchronous powerpc processors with user-configurable address space provided. new embedded amba ? specification 2.0 ahb sys- tem bus ( arm ? processor) facilitates communica- tion among the microprocessor interface, configuration logic, embedded block ram, fpga logic, and embedded standard cell blocks. new network plls meet itu-t g.811 specifications and provide clock conditioning for ds-1/e-1 and sts-3/stm-1 applications. flexible general purpose pplls offer clock multiply (up to 8x), divide (down to 1/8x), phase shift, delay compensation, and duty cycle adjustment combined. variable size bused readback of configuration data capability with the built-in microprocessor interface and system bus. internal, 3-state, and bidirectional buses with simple control provided by the slic. new clock routing structures for global and local clocking significantly increases speed and reduces skew (<200 ps for or4e4). new local clock routing structures allow creation of localized clock trees. new double-data rate (ddr) and zero-bus turn- around (zbt) memory interfaces support the latest high-speed memory interfaces. new 2x/4x uplink and downlink i/o capabilities inter- face high-speed external i/os to reduced speed internal logic. orca foundry 2000 development system software. supported by industry-standard cae tools for design entry, synthesis, simulation, and timing analysis. meets universal test and operations phy interface for atm (utopia) levels 1, 2, and 3; as well as pos-phy3. also meets proposed specifications for utopia level 4 and pos-phy3 (2.5 gbits/s) and pos-phy4 (10 gbits/s) interface standards for packet-over-sonet as defined by the saturn group. two new edge clock routing structures allow up to seven high-speed clocks on each edge of the device for improved setup/hold and clock to out perfor- mance.
agere systems inc. 7 preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel description what is an fpsc? fpscs, or field-programmable system chips, are devices that combine field-programmable logic with asic or mask-programmed logic on a single device. fpscs provide the time to market and the flexibility of fpgas, the design effort savings of using soft intellec- tual property (ip) cores, and the speed, design density, and economy of asics. fpsc overview agere ? s series 4 fpscs are created from series 4 orca fpgas. to create a series 4 fpsc, several col- umns of programmable logic cells (see fpga logic overview section for fpga logic details) are added to an embedded logic core. other than replacing some fpga gates with asic gates, at greater than 10:1 effi- ciency, none of the fpga functionality is changed ? all of the series 4 fpga capability is retained: embedded block rams, mpi, pcms, boundary scan, etc. the col- umns of programmable logic are replaced at the right of the device, allowing pins from the replaced columns to be used as i/o pins for the embedded core. the remainder of the device pins retain their fpga func- tionality. the embedded cores can take many forms and gener- ally come from agere ? s asic libraries. other offerings allow customers to supply their own core functions for the creation of custom fpscs. fpsc gate counting the total gate count for an fpsc is the sum of its embedded core (standard-cell/asic gates) and its fpga gates. because fpga gates are generally expressed as a usable range with a nominal value, the total fpsc gate count is sometimes expressed in the same manner. standard-cell asic gates are, however, 10 to 25 times more silicon-area efficient than fpga gates. therefore, an fpsc with an embedded function is gate equivalent to an fpga with a much larger gate count. fpga/embedded core interface the interface between the fpga logic and the embed- ded core has been enhanced to allow for a greater number of interface signals than on previous fpsc architectures. compared to bringing embedded core signals off-chip, this on-chip interface is much faster and requires less power. all of the delays for the inter- face are precharacterized and accounted for in the orca foundry development system. series 4 based fpscs expand this interface by provid- ing a link between the embedded block and the multi- master 32-bit system bus in the fpga logic. this sys- tem bus allows the core easy access to many of the fpga logic functions including the embedded block rams and the microprocessor interface. clock spines also can pass across the fpga/embed- ded core boundary. this allows for fast, low-skew clock- ing between the fpga and the embedded core. many of the special signals from the fpga, such as done and global set/reset, are also available to the embed- ded core, making it possible to fully integrate the embedded core with the fpga as a system. for even greater system flexibility, fpga configuration rams are available for use by the embedded core. this allows for user-programmable options in the embedded core, in turn allowing for greater flexibility. multiple embedded core configurations may be designed into a single device with user-programmable control over which configurations are implemented, as well as the capability to change core functionality simply by recon- figuring the device. orca foundry 2000 development system the orca foundry 2000 development system is used to process a design from a netlist to a configured fpga. this system is used to map a design onto the orca architecture, and then place and route it using orca foundry ? s timing-driven tools. the development system also includes interfaces to, and libraries for, other popular cae tools for design entry, synthesis, simulation, and timing analysis. the orca foundry 2000 development system inter- faces to front-end design entry tools and provides the tools to produce a configured fpga. in the design flow, the user defines the functionality of the fpga at two points in the design flow: design entry and the bit- stream generation stage. recent improvements in orca foundry allow the user to provide timing requirement information through logical preferences only; thus, the designer is not required to have physical knowledge of the implementation.
8 8 agere systems inc. preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel description (continued) following design entry, the development system ? s map, place, and route tools translate the netlist into a routed fpga. a floorplanner is available for layout feedback and control. a static timing analysis tool is provided to determine device speed and a back-annotated netlist can be created to allow simulation and timing. timing and simulation output files from orca foundry are also compatible with many third-party analysis tools. its bit stream generator is then used to generate the configuration data which is loaded into the fpgas internal configuration ram, embedded block ram, and/or fpsc memory. when using the bit stream generator, the user selects options that affect the functionality of the fpga. com- bined with the front-end tools, orca foundry pro- duces configuration data that implements the various logic and routing options discussed in this data sheet. fpsc design kit development is facilitated by an fpsc design kit which, together with orca foundry and third-party synthesis and simulation engines, provides all software and documentation required to design and verify an fpsc implementation. included in the kit are the fpsc configuration manager, synopsys smart model ? , and complete online documentation. the kit's software cou- ples with orca foundry, providing a seamless fpsc design environment. more information can be obtained by visiting the orca website or contacting a local sales office, both listed on the last page of this docu- ment. fpga logic overview the orca series 4 architecture is a new generation of sram-based programmable devices from agere. it includes enhancements and innovations geared toward today ? s high-speed systems on a single chip. designed with networking applications in mind, the series 4 fam- ily incorporates system-level features that can further reduce logic requirements and increase system speed. orca series 4 devices contain many new patented enhancements and are offered in a variety of packages and speed grades. the hierarchical architecture of the logic, clocks, rout- ing, ram, and system-level blocks create a seamless merge of fpga and asic designs. modular hardware and software technologies enable system-on-chip inte- gration with true plug-and-play design implementation. the architecture consists of four basic elements: pro- grammable logic cells (plcs), programmable i/o cells (pios), embedded block rams (ebrs), and system- level features. these elements are interconnected with a rich routing fabric of both global and local wires. an array of plcs are surrounded by common interface blocks which provide an abundant interface to the adja- cent plcs or system blocks. routing congestion around these critical blocks is eliminated by the use of the same routing fabric implemented within the pro- grammable logic core. each plc contains a pfu, slic, local routing resources, and configuration ram. most of the fpga logic is performed in the pfu, but decoders, pa l -like functions, and 3-state buffering can be performed in the slic. the pios provide device inputs and outputs and can be used to register signals and to perform input demultiplexing, output multiplex- ing, uplink and downlink functions, and other functions on two output signals. large blocks of 512 x 18 quad- port ram complement the existing distributed pfu memory. the ram blocks can be used to implement ram, rom, fifo, multiplier, and cam. some of the other system-level functions include the mpi, plls, and the embedded system bus (esb). plc logic each pfu within a plc contains eight 4-input (16-bit) luts, eight latches/ffs, and one additional flip-flop that may be used independently or with arithmetic func- tions. the pfu is organized in a twin-quad fashion; two sets of four luts and ffs that can be controlled indepen- dently. each pfu has two independent programmable clocks, clock enables, local set/reset, and data selects. luts may also be combined for use in arithmetic func- tions using fast-carry chain logic in either 4-bit or 8-bit modes. the carry-out of either mode may be registered in the ninth ff for pipelining. each pfu may also be configured as a synchronous 32 x 4 single- or dual-port ram or rom. the ffs (or latches) may obtain input from lut outputs or directly from invertible pfu inputs, or they can be tied high or tied low. the ffs also have programmable clock polarity, clock enables, and local set/reset.
agere systems inc. 9 preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel description (continued) the slic is connected from plc routing resources and from the outputs of the pfu. it contains eight 3-state, bidirectional buffers, and logic to perform up to a 10-bit and function for decoding, or an and-or with optional invert to perform pa l -like functions. the 3-state drivers in the slic and their direct connections from the pfu outputs make fast, true, 3-state buses possible within the fpga, reducing required routing and allowing for real-world system performance. programmable i/o the series 4 pio addresses the demand for the flexi- bility to select i/os that meet system interface require- ments. i/os can be programmed in the same manner as in previous orca devices, with the additional new features which allow the user the flexibility to select new i/o types that support high-speed interfaces. each pio contains four programmable i/o pads and is interfaced through a common interface block to the fpga array. the pio is split into two pairs of i/o pads with each pair having independent clock enables, local set/reset, and global set/reset. on the input side, each pio contains a programmable latch/flip-flop which enables very fast latching of data from any pad. the combination provides for very low setup requirements and zero hold times for signals coming on-chip. it may also be used to demultiplex an input signal, such as a multiplexed address/data signal, and register the sig- nals without explicitly building a demultiplexer with a pfu. on the output side of each pio, an output from the plc array can be routed to each output flip-flop, and logic can be associated with each i/o pad. the output logic associated with each pad allows for multiplexing of out- put signals and other functions of two output signals. the output ff, in combination with output signal multi- plexing, is particularly useful for registering address signals to be multiplexed with data, allowing a full clock cycle for the data to propagate to the output. the out- put buffer signal can be inverted, and the 3-state con- trol can be made active-high, active-low, or always enabled. in addition, this 3-state signal can be regis- tered or nonregistered. the series 4 i/o logic has been enhanced to include modes for speed uplink and downlink capabilities. these modes are supported through shift register logic, which divides down incoming data rates or multi- plies up outgoing data rates. this new logic block also supports high-speed ddr mode requirements where data is clocked into and out of the i/o buffers on both edges of the clock. the new programmable i/o cell allows designers to select i/os which meet many new communication stan- dards permitting the device to hook up directly without any external interface translation. they support tradi- tional fpga standards as well as high-speed, single- ended, and differential-pair signaling (as shown in table 1). based on a programmable, bank-oriented i/o ring architecture, designs can be implemented using 3.3 v, 2.5 v, 1.8 v, and 1.5 v referenced output levels. routing the abundant routing resources of the series 4 archi- tecture are organized to route signals individually or as buses with related control signals. both local and global signals utilize high-speed buffered and nonbuffered routes. one plc segmented (x1), six plc segmented (x6), and bused half chip (xhl) routes are patterned together to provide high connectivity with fast software routing times and high-speed system performance. eight fully distributed primary clocks are routed on a low-skew, high-speed distribution network and may be sourced from dedicated i/o pads, plls, or the plc logic. secondary and edge-clock routing is available for fast regional clock or control signal routing for both internal regions and on device edges. secondary clock routing can be sourced from any i/o pin, plls, or the plc logic. the improved routing resources offer great flexibility in moving signals to and from the logic core. this flexibil- ity translates into an improved capability to route designs at the required speeds when the i/o signals have been locked to specific pins.
10 10 agere systems inc. preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel system-level features the series 4 also provides system-level functionality by means of its microprocessor interface, embedded sys- tem bus, quad-port embedded block rams, universal programmable phase-locked loops, and the addition of highly tuned networking specific phase-locked loops. these functional blocks allow for easy glueless system interfacing and the capability to adjust to varying condi- tions in today ? s high-speed networking systems. microprocessor interface the mpi provides a glueless interface between the fpga and powerpc microprocessors. programmable in 8-, 16-, and 32-bit interfaces with optional parity to the motorola ? powerpc 860 bus, it can be used for configuration and readback, as well as for fpga con- trol and monitoring of fpga status. all mpi transac- tions utilize the series 4 embedded system bus at 66 mhz performance. a system-level microprocessor interface to the fpga user-defined logic following configuration, through the system bus, including access to the embedded block ram and general user-logic, is provided by the mpi. the mpi supports burst data read and write transfers, allowing short, uneven transmission of data through the interface by including data fifos. transfer accesses can be single beat (1 x 4 bytes or less), 4-beat (4 x 4 bytes), 8-beat (8 x 2 bytes), or 16-beat (16 x 1 bytes). system bus an on-chip, multimaster, 8-bit system bus with 1-bit parity facilitates communication among the mpi, config- uration logic, fpga control, and status registers, embedded block rams, as well as user logic. utilizing the amba specification rev 2.0 ahb protocol, the embedded system bus offers arbiter, decoder, master, and slave elements. master and slave elements are also available for the user-logic and embedded back- plane transceiver portion of the ort82g5. the system bus control registers can provide control to the fpga such as signaling for reprogramming, reset functions, and pll programming. status registers mon- itor init, done, and system bus errors. an interrupt controller is integrated to provide up to eight possible interrupt resources. bus clock generation can be sourced from the microprocessor interface clock, con- figuration clock (for slave configuration modes), internal oscillator, user clock from routing, or from the port clock (for jtag configuration modes). phase-locked loops up to eight plls are provided on each series 4 device, with four plls generally provided for fpscs. program- mable plls can be used to manipulate the frequency, phase, and duty cycle of a clock signal. each ppll is capable of manipulating and conditioning clocks from 20 mhz to 420 mhz. frequencies can be adjusted from 1/8x to 8x, the input clock frequency. each programma- ble pll provides two outputs that have different multi- plication factors but can have the same phase relationships. duty cycles and phase delays can be adjusted in 12.5% of the clock period increments. an automatic input buffer delay compensation mode is available for phase delay. each ppll provides two out- puts that can have programmable (12.5% steps) phase differences. additional highly tuned and characterized, dedicated phase-locked loops (dplls) are included to ease sys- tem designs. these dplls meet itu-t g.811 primary- clocking specifications and enable system designers to very tightly target specified clock conditioning not tradi- tionally available in the universal pplls. initial dplls are targeted to low-speed networking ds1 and e1, and also high-speed sonet/sdh networking sts-3 and stm-1 systems. these dplls are not typically included on fpsc devices and are not found on the ort82g5. embedded block ram new 512 x 18 quad-port ram blocks are embedded in the fpga core to significantly increase the amount of memory and complement the distributed pfu memo- ries. the ebrs include two write ports, two read ports, and two byte lane enables which provide four-port operation. optional arbitration between the two write ports is available, as well as direct connection to the high-speed system bus. additional logic has been incorporated to allow signifi- cant flexibility for fifo, constant multiply, and two-vari- able multiply functions. the user can configure fifo blocks with flexible depths of 512k, 256k, and 1k includ- ing asynchronous and synchronous modes and pro- grammable status and error flags. multiplier capabilities allow a multiple of an 8-bit number with a 16-bit fixed coefficient or vice versa (24-bit output), or a multiply of two 8-bit numbers (16-bit output). on-the-fly coefficient modifications are available through the second read/ write port. two 16 x 8-bit cams per embedded block can be implemented in single match, multiple match, and clear modes. the ebrs can also be preloaded at device configuration time.
agere systems inc. 11 preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel system-level features (continued) configuration the fpgas functionality is determined by internal con- figuration ram. the fpgas internal initialization/con- figuration circuitry loads the configuration data at powerup or under system control. the configuration data can reside externally in an eeprom or any other storage media. serial eeproms provide a simple, low pin-count method for configuring fpgas. the ram is loaded by using one of several configura- tion modes. supporting the traditional master/slave serial, master/slave parallel, and asynchronous periph- eral modes, the series 4 also utilizes its microproces- sor interface and embedded system bus to perform both programming and readback. daisy chaining of multiple devices and partial reconfiguration are also permitted. other configuration options include the initialization of the embedded-block ram memories and fpsc mem- ory as well as system bus options and bit stream error checking. programming and readback through the jtag (ieee 1149.2 ) port is also available meeting in- system programming (isp) standards ( ieee 1532 draft). additional information contact your local agere representative for additional information regarding the orca series 4 fpga devices, or visit our website at: http://www.agere.com/orca ort82g5 overview device layout the ort82g5 is a backplane transceiver fpsc with embedded cdr and serdes circuitry and 8b/10b encoding/decoding. it is intended for high-speed serial backplane data transmission. built using series 4 reconfigurable system-on-chips (soc) architecture, it also contains up to 400k usable fpga system gates. the ort82g5 contains an fpga base array, an eight- channel clock and data recovery macro, and an eight- channel 8b/10b interface on a single monolithic chip. version ii of this device, which will be plug-in compati- ble to version i, also adds sonet scrambling capabil- ity. the version ii features are not described in this data sheet. figure 1 shows the ort82g5 block diagram. boundary scan for the ort82g5 only includes pro- grammable i/os and does not include any of the embedded block i/os. backplane transceiver interface the ort82g5 backplane transceiver fpsc has eight channels, each operating at up to 3.125 gbits/s (2.5 gbits/s data rate) with a full-duplex synchronous interface with built-in clock recovery (cdr). the cdr macro with 8b/10b provides guaranteed ones density for the cdr, byte alignment, and error detection. the cdr interface provides a physical medium for high-speed asynchronous serial data transfer between system devices. devices can be on the same pc- board, on separate boards connected across a back- plane, or connected by cables. this core is intended for, but not limited to, terminal equipment in sonet/ sdh, gbit ethernet, 10 gbit ethernet, atm, fibre-chan- nel, and infiniband systems. the serdes circuitry consists of receiver, transmitter, and auxiliary functional blocks. the receiver accepts high-speed (up to 3.125 gbits/s) serial data. based on data transitions the receiver locks an analog receive pll for each channel to retime the data, then demulti- plexes down to parallel bytes and clock. the transmitter operates in the reverse direction. parallel bytes are multiplexed up to 3.125 gbits/s serial data for off-chip communication. the transmitter generates the neces- sary 3.125 ghz clocks for operation from a lower speed reference clock. this device will support 8b/10b encoding/decoding, which is capable of frame synchronization and physical link monitoring. figure 2 shows the internal architec- ture of the ort82g5 backplane transceiver core.
12 agere systems inc. preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel ort82g5 overview (continued) 1023(f) figure 1. ort82g5 block diagram standard orca series 4 fpga logic 8-bit/10-bit encoder 8-bit/10-bit decoder clock/data recovery byte- wide data cml 8 full- 3.125 gbits/s fpga i/os data duplex serial channels i/os psudo- sonet framer scrambling fifo alignment selected toh (version 2) to 1.0 gbits/s 3.125 gbits/s data to 1.0 gbits/s
agere systems inc. 13 preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel ort82g5 overview (continued) 2262(f) figure 2. internal high-level diagram of ort82g5 transceiver serdes high-speed data 1:10 3.125 ? 2.5 ? 2.0 ? 1.25 ? 1.0 gbits/s quad channel demultiplexer 10:1 multiplexer quad channel mux/demux 1:4 demultiplexer 4:1 multiplexer multi-channel alignment and fifo 2 to 1 data selector low speed data 25 ? 78 mbits/s clock 25 ? 78 mhz 10:1 multiplexer 1:10 demultiplexer quad channel mux/demux 4:1 multiplexer 1:4 demultiplexer multi-channel alignment and fifo 2 to 1 data selector low speed data 25 ? 78 mbits/s clock 25 ? 78 mhz reference clock reference clock micro- processor interface and registers system bus signals 4k x 36 dual port ram 4k x 36 dual port ram data and control fpga logic and ios high-speed data 3.125 ? 2.5 ? 2.0 ? 1.25 ? 1.0 gbits/s (with 8b/10b encoder/decoder) serdes quad channel (with 8b/10b encoder/decoder) (auxiliary block)
14 14 agere systems inc. preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel ort82g5 overview (continued) the ort82g5 fpsc combines 8 channels of high- speed full duplex serial links (up to 3.125 gbits/s) with 400k usable gate fpga. the major functional blocks in the asb core are two quad-channel serializer-deserial- izers (serdes) including 8b/10b encoder/decoder and dedicated plls, xaui or fibre-channel link-state- machine, 4-to-1 or 1-to-4 mux/demux, multichannel alignment fifo, microprocessor interface, and 4k x 36 ram blocks. serializer and deserializer (serdes) the serdes block is a quad transceiver for serial data transmission, with a selectable data rate of 1.0 ? 1.25 gbits/s, 2.0 ? 2.5 gbits/s, or 3.125 gbits/s. it is designed to operate in ethernet, fibre channel, firewire ? , or backplane applications. it features high- speed 8b/10b parallel i/o interfaces, and high-speed cml interfaces. the quad transceiver is controlled and configured with an 8 bit microprocessor interface through the fpga. each channel has dedicated registers that are readable and writable. the quad device also contains global reg- isters for control of common circuitry and functions. for complete serdes description, please refer to the macrocell data sheet, lu6x14ft1.0-1.25/2.0-2.5/ 3.125 gbits/s serializer and deserializer . 8b/10b encoding/decoding the ort82g5 facilitates high-speed serial transfer of data in a variety of applications including gbit ethernet, fibre channel, serial backplanes, and proprietary links. the serdes provides 8b/10b coding/decoding for each channel. the 8b/10b transmission code includes serial encoding/decoding rules, special characters, and error detection. in the receive direction, the user can disable the 8b/10b decoder to receive raw 10 bit words which will be rate reduced by the serdes. if this mode is chosen, the user must bypass the multichannel alignment fifos. in the transmit direction, the 8b/10b encoder must always be enabled (version ii will allow it to be disabled). clocks the serdes block contains its own dedicated plls for transmit and receive clock generation. the user pro- vides a reference clock of the appropriate frequency. the receiver plls extract the clock from the serial input data and retime the data with the recovered clock. mux/demux block the purpose of the mux/demux block is to provide a wide, low-speed interface at the fpga portion of the ort82g5 for each channel or data lane. the interface to the serdes macro runs at 1/10th the bit rate of the data lane. the mux/demux converts the data rate and bit-width so the fpga core can run at 1/4th this frequency. this implies a range of 25 ? 78 mhz for the data in and out of the fpga. the mux/demux block in the ort82g5 is a 4-channel block. it provides an interface between each quad channel serdes and the fpga logic. multichannel alignment fifos the ort82g5 has a total of 8 channels (4 per ser- des). the incoming data of these channels can be synchronized in several ways, or they can be indepen- dent of one other. for example, all four channels in a serdes can be aligned together to form a communication channel with a bandwidth of 10 gbits/s. alternatively, two channels within a serdes can be aligned together; channel a and b and/or channel c and d. optionally, the alignment can be extended across ser- des to align all 8 channels. individual channels within an alignment group can be disabled (i.e., power down) without disrupting other channels. xaui or fibre-channel link state machine two separate link state machines are included in the ort82g5. a xaui compliant link state machine is included in the embedded core to implement the ieee 802.3ae v2.1 standard. a separate state machine for fibre-channel/ infiband is also provided. dual port rams there are two independent memory blocks in the asb. each memory block has a capacity of 4k word by 36 bits. it has one read port, one write port, and four byte-write-enable (active-low) signals. the read data from the memory block is registered so that it works as a pipelined synchronous memory block.
agere systems inc. 15 preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel ort82g5 overview (continued) fpga interface the fpga logic will receive/transmit frame-aligned (optional for 8b/10b mode) 32-bit streams of up to 77.8 mhz data (maximum of eight streams in each direction) from/to the embedded core. all frames trans- mitted to the fpga can be aligned using comma char- acters or code violation from each channel, and a single aligned frame pulse is provided to the fpga logic for each group of aligned channels. for transmit, the generation of a comma or code violation that can be found by the receiving device on the other side of the serial link is created through an independent con- trol signal per channel. if the receive channel alignment fifos are bypassed, then each channel will provide its own receive clock and k character detect signals. if the 8b/10b decoders are bypassed, then 40-bit data streams are passed to the fpga logic. no frame pulses are available in this case and channel alignment cannot be performed. fpsc configuration configuration of the ort82g5 occurs in two stages: fpga bitstream configuration and embedded core setup. fpga configuration prior to becoming operational, the fpga goes through a sequence of states, including powerup, initialization, configuration, start-up, and operation. the fpga logic is configured by standard fpga bit stream configura- tion means as discussed in the series 4 fpga data sheet. the options for the embedded core are set via registers that are accessed through the fpga system bus. the system bus can be driven by an external pow- erpc compliant microprocessor via the mpi block or via a user master interface in fpga logic. a simple ip block, that drives the system by using the user register interface and very little fpga logic, is available in the mpi/system bus application note . this ip block sets up the embedded core via a state machine and allows the ort82g5 to work in an independent system with- out an external microprocessor interface. backplane transceiver core detailed description serdes a detailed block diagram of the receive and transmit data paths for a single channel of the serdes is shown in figure 3. the transmitter section accepts either 8-bit unencoded data or 10-bit encoded data at the parallel input port. it also accepts the low-speed reference clock at the ref- clk input and uses this clock to synthesize the internal high-speed serial bit clock. the serialized data are available at the differential cml output terminated in 50 ? or 75 ? to drive either an optical transmitter or coaxial media or circuit board/backplane. the receiver section receives high-speed serial data at its differential cml input port. these data are fed to the clock recovery section which generates a recovered clock and retimes the data. this means that the receive clocks are asynchronous between channels. the retimed data are deserialized and presented as a 10-bit encoded or a 8-bit unencoded parallel data on the out- put port. two-phase receive byte clocks are available synchronous with the parallel words. the receiver also optionally recognizes the comma characters or code violations and aligns the bit stream to the proper word boundary. bias section a fractional band-gap voltage generator is included on the design. an external resistor (3.32 k ? 1%), con- nected between the pins rext and vssrext gener- ates the bias currents within the chip. this resistor should be able to handle at least 300 a.
16 agere systems inc. preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel backplane transceiver core detailed description (continued) reset operation the serdes block can be reset in one of three different ways as follows: on power up, using the hardware reset, or via the microprocessor interface. the power up reset process begins when the power supply voltage ramps up to approximately 80% of the nominal value of 1.5 v. following this event, the device will be ready for normal operation after 3 ms. a hardware reset is initiated by making the pasb_resetn low for at least two microprocessor clock cycles. the device will be ready for operation 3 ms after the low to high transition of the pasb_resetn. this reset function affects all serdes channels and resets all microprocessor and internal registers and counters. using the software reset option, each channel can be individually reset by setting swrst (bit 2) to a logic 1 in the channel configuration register. the device will be ready 3 ms after the swrst bit is deasserted. similarly, all four channels per quad serdes can be reset by setting the global reset bit gswrst. the device will be ready for nor- mal operation 3 ms after the gswrst bit is deasserted. note that the software reset option resets only serdes internal registers and counters. the microprocessor registers are not affected. it should also be noted that the embedded block cannot be accessed until after fpga configuration is complete. start up sequence 1. initiate a hardware reset by making pasb_resetn low for 100 ns. the device will be ready for operation 3 ms after the low to high transition of pasb_resetn. during this time configure the fpga portion of the device. 2. wait for 100 ns. configure the following serdes internal and external registers. set the following bits in register 30800: ? bits lckrefn_[ad:aa] to 1, which implies lock to data. ? bits enbysync_[ad:aa] to 1 which enables dynamic alignment to comma. set the following bits in register 30801: ? bits loopenb_[ad:aa] to 1 if loopback is desired. set the following bits in register 30900: ? bits lckrefn_[bd:ba] to 1 which implies lock to data. ? bits enbysync_[bd:ba] to 1 which enables dynamic alignment to comma. set the following bits in register 30901: ? bits loopenb_[bd:ba] to 1 if loopback is desired. set the following bits in registers 30002, 30012, 30022, 30032, 30102, 30112, 30122, 30132: ? txhr[0:3] set to 1 if tx half-rate is desired. ? 8b10bt[0:1] set to 1 set the following bits in registers 30003, 30013, 30023, 30033, 30103, 30113, 30123, 30133: ? rxhr[0:3] set to 1 if rx half-rate is desired. ? 8b10br[0:3] set to 1. monitor the following alarm bits in registers 30000, 30010, 30020, 30030, 30110, 30120, 30130: ? lki-pll lock indicator. 1 indicates that pll has achieved lock. ? sdon-signal detect output indicator. 0 indicates active data.
agere systems inc. 17 preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel backplane transceiver core detailed description (continued) 2263(f) figure 3. serdes functional block diagram for one channel 10-bit register 8b/10b encoder link state 8b/10b decoder machine transmit pll receive pll serial to parallel byte aligner mux mux preemphasis to/from mux/demux block hdinp_(a,b)(a-d) hdinn_(a,b)(a-d) parallel to serial hdoutp_(a,b)(a-d) hdoutn_(a,b)(a-d) refclkp_(a,b) refclkn_(a,b) srbd(a-d) [9:0] swdsync srbc0 srbc1 sbytsync stbd(a-d) [9:0] prbs generator prbs checker activity detector stbc311 (a-d) (a-d) (a-d) (a-d) (a-d) scv (a-d)
18 agere systems inc. preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel backplane transceiver core detailed description (continued) serdes transmit path (fpga backplane) the transmitter section accepts either 8-bit unencoded data or 10-bit encoded data at the parallel input port from the mux/demux block. it also accepts the low-speed reference clock at the refclk input and uses this clock to synthesize the internal high-speed serial bit clock. the serialized data are available at the differential cml output terminated in 50 ? or 75 ? to drive either an optical transmitter, coaxial media, or circuit board/backplane. the stbdx[8:0] (where x is a placeholder for one of the letters, a ? d) ports carry unencoded character data in this design. the time-division multiplexer in the ort82g5 is only 9 bits wide. the 10th bit (stbdx[9]) of each data lane into the serdes is held constant. it is not possible to use the ort82g5 for normal data communication without enabling serdes 8b/10b encoding. the functional mode uses the stbcx311 serdes output as the reference clock. the frequency of this clock will depend on the half-rate/full-rate control bit in the serdes; and the frequency of the refclk ports and/or that of the high-speed serial data. the serdes tbcksel control bit must be configured to a 0 for each channel in order for this clocking strategy to work. a falling edge on the stbc311x clock port will cause a new data character to be sent from stbdx[9:0] to the ser- des block with a latency of 5 stbc311x clock cycles at the high-speed serial output. 2264(f) figure 4. ort82g5 transmit path for a single serdes channel 10:1 multiplexer 100 ? 156 mhz pll 8b/10b encoder clock transmit data 1.0 ? 3.125 gbits/s 4:1 multiplexer (x 9) 10 8 reference embedded core data byte stbdx[7:0] k-control stbdx{8] 9 ground stbdx[9] stbc311x serdes mux/demux hdoutpx, hdoutnx pq r s t xyz stbdx[9:0] stbc311x hdoutx p 4 p 5 p 6 p 7 p 8 p 9 p 0 p 1 p 2 p 3 latency = 5 stbc311x clocks block block
agere systems inc. 19 preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel backplane transceiver core detailed description (continued) transmit preemphasis and amplitude control the transmitter ? s cml output buffer is terminated on-chip to optimize the data eye as well as to reduce the number of discrete components required. the differential output swing reaches a maximum of 1.2 v pp in the normal ampli- tude mode. a half amplitude mode can be selected via configuration register bit hamp. half amplitude mode can be used to reduce power dissipation when the transmission medium has minimal attenuation. a programmable preemphasis circuit is provided to boost the high frequencies in the transmit data signal to maxi- mize the data eye opening at the far-end receiver. preemphasis is particularly useful when the data are transmitted over backplanes or low-quality coax cables. the degree of preemphasis can be programmed with a two-bit control from the microprocessor interface as shown in table 2. the high-pass transfer function of the preemphasis circuit is shown below, where the value of a is shown in table 2. h(z) = (1 ? az ? 1 ) table 2. preemphasis settings serdes receive path (backplane fpga) the receiver section receives high-speed serial data at its differential cml input port. these data are fed to the clock recovery section which generates a recovered clock and retimes the data. this means that the receive clocks are asynchronous between channels. the retimed data are deserialized and presented as a 10-bit encoded or a 8-bit unencoded parallel data on the output port. two-phase receive byte clocks are available synchronous with the parallel words. the receiver also recognizes the comma characters and aligns the bit stream to the proper word boundary. the receive pll has two modes of operation as follows: lock to reference and lock to data with retiming. when no data or invalid data is present on the hdinp and hdinn pins, the receive vco will not lock to data and its fre- quency can drift outside of the nominal 100 ppm range. under this condition, the receive pll will lock to refclk for a fixed time interval and then will attempt to lock to receive data. the process of attempting to lock to data, then locking to clock will repeat until valid input data exists. there is also a control register bit per channel to force the receive pll to always lock to the reference clock. the activity detector monitors the presence of data on each of the differential high-speed input pins. in the absence of amplitude qualified data on the inputs the chip automatically goes into sleep mode. this function can, however, be disabled through the control interface. the prbs checker is a built-in bit error rate tester (bert). when enabled, it produces a one-bit prbschk output to indicate whether there was an error in the loopback data. pe1 pe0 amount of preemphasis (a) 0 0 0% (no preemphasis) 01 12.5% 10 12.5% 1 1 25%
20 agere systems inc. preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel backplane transceiver core detailed description (continued) data from a serdes channel appears in 10-bit raw form or 8-bit decoded form at the srbdx[9:0] port (where x is a placeholder for one of the letters, a-d) with a latency of approximately 14 cycles. accompanying this data are the comma-character indicator (sbytsyncx), clocks (srbc0x, and srbc1x), link-state indicator (swdsyncx), and code-violation indicator (scvx). with the 8b10br control bit of the serdes channel set to 1, the data presented at srbdx[9:0] will be decoded characters. bit 8 will indicate whether srbdx[7:0] represents an ordinary data character (bit 8 == 0), or whether srbdx[7:0] represents a special character, like a comma. when 8b10br is set to 0, the data at srbdx[9:0] will be encoded characters. the xaui link-state machine should not be used in this mode of operation. when in xaui mode, the mux/demux looks for /a/ (as defined in ieee 802.3ae v.2.1) characters for channel alignment and requires the characters to be in decoded form for this to work. 2265(f) figure 5. ort82g5 receive path for a single serdes channel 8b/10b encoder 100 ? 156 mhz pll & cdr clock hdinpx, receive data 1.0 ? 3.125 gbits/s 1:4 multiplexer (x 10) xaui link reference embedded core 10:1 multiplexer code group alignment link state machine srbdx[9:0] state sbytsyncx srbc0x scvx machine 25 ? 78 mhz clock commadet 4 k_ctrl 32 data multi-channel alignment fifo 2:1 multiplexer (x 40) data 40 data 36 serdes mux/demux channel align swdsyncx srbc1x hdinnx pqrs t xyz srbdx[9:0] srbc0x srbc1x sbytsyncx, svcx swdsyncx q 0 r 8 r 9 s 0 p 4 p 5 p 6 p 7 p 8 p 9 p 0 p 1 p 2 p 3 r 2 r 3 r 4 r 5 r 6 r 7 s 1 s 2 s 3 s 4 p hdinx srbdx[9:0] 1-bit 10-bit de- block block block latency = approx 23 clocks
agere systems inc. 21 preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel backplane transceiver core detailed description (continued) 8b/10b encoding/decoding the 8b/10b encoder encodes the incoming 8-bit data into a 10-bit format according to the ieee 802.3z stan- dard. input pins srbdx<7:0> (where x is a placeholder for one of the letters, a ? d) are used for 8 bit unen- coded data and srbdx<8> is used as the k_control input to indicate whether the 8 data bits need to be encoded as special characters (k_control = 1) or as data characters (k_control = 0). when the encoder is bypassed srbdx<9:0>serve as the data bits for the 10-bit encoded data. within the definition of the 8b/10b transmission code, the bit positions of the 10-bit encoded transmission characters are labeled as a, b, c, d, e, i, f, g, h, and j in that order. bit a corresponds to srbdx[0], bit b to srbdx[1], bit c to srbdx[2], bit d to srbdx[3], bit e to srbdx[4], bit i to srbdx[5], bit f to srbdx[6], bit g to srbdx[7], bit h to srbdx[8], and bit j to srbdx[9]. the data srbdx[9:0] is transmitted serially with srbdx[0] transmitted first and srbdx[9] transmitted last. for an 8-bit unencoded data, the 8-bit unencoded data srdbx[7:0] is represented as hgf edcba srdbx[8] represents the k_ctrl bit and srdbx[9] is unused (tied to logic 0). srbdx[0] is still transmitted first and srbdx[9] transmitted last. serdes transmit and receive plls the high-speed transmit and receive serial data can operate at 1.0 ? 1.25 gbits/s or 2.0 ? 3.125 gbits/s depending on the state of the control bits from the microprocessor interface. table 3 shows the relation- ship between the data rates, the reference clock, and the transmit twckx clocks. the receiver section receives high-speed serial data at its differential cml input port. these data are fed to the clock recovery section which generates a recovered clock and retimes the data. this means that the receive clocks are asynchronous between channels. the retimed data are deserialized and presented as a 10-bit encoded or a 8-bit unencoded parallel data on the out- put port. rwckx receive byte clocks are available syn- chronous with the parallel words. the receiver also recognizes the comma characters and aligns the bit stream to the proper word boundary. table 4 shows the relationship between the data rates, the reference clock, and the rwckx clocks. for more information on the reference clock input requirements and connections to either single ended or differential inputs, see the lu6x14ft serdes macro- cell data sheet or the associated reference clock appli- cation note. table 3. transmit pll clock and data rates note: the selection of full-rate or half-rate for a given reference clock speed is set by a bit in the transmit control register and can be set per channel. table 4. receive pll clock and data rates note: the selection of full-rate or half-rate for a given reference clock speed is set by a bit in the receive control register and can be set per channel. reference clock the differential reference clock is distributed to all four channels. each channel has a differential buffer to iso- late the clock from the other channels. the input clock is preferably a differential signal; however, the device can operate with a single-ended input. the input refer- ence clock directly impacts the transmit data eye, so the clock should have low jitter. in particular, jitter com- ponents in the dc ? 5 mhz range should be minimized. note: the reference clock, refclk, is equivalent to refinp and refinn; throughout the text simply refer to the reference clock as refclk. data rate reference clock tck78[a, b] clock rate 1.0 gbits/s 100 mhz 25 mhz half 1.25 gbits/s 125 mhz 31.25 mhz half 2.0 gbits/s 100 mhz 50 mhz full 2.5 gbits/s 125 mhz 62.5 mhz full 3.125 gbits/s 156 mhz 78 mhz full data rate reference clock rwckx clocks rate 1.0 gbits/s 100 mhz 25 mhz half 1.25 gbits/s 125 mhz 31.25 mhz half 2.0 gbits/s 100 mhz 50 mhz full 2.5 gbits/s 125 mhz 62.5 mhz full 3.125 gbits/s 156 mhz 78 mhz full
22 22 agere systems inc. preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel backplane transceiver core detailed description (continued) byte alignment when enbysync = 1, the ort82g5 recognizes the comma sequence and aligns the 10-bit comma con- taining character to the word boundary. bytsync = 1 when the parallel output word contains a byte-aligned comma containing character. the bytsync flag will continue to pulse a logic 1 whenever a byte aligned comma containing character is at the parallel output port. link state machines two link state machines are included in the ort82g5, one for xaui applications and a second for fibre-chan- nel applications. the fibre-channel link state machine is responsible for establishing a valid link between the transmitter and the receiver and for maintaining link synchronization. the machine wakes up in the loss of synchronization state upon powerup reset. this is indicated by wdsync = 0. while in this state, the machine looks for a particular number of consecutive idle ordered sets without any invalid data transmission in between before declaring synchronization achieved. synchronization achieved is indicated by asserting wdsync = 1. spe- cifically, the machine looks for three continuous idle ordered sets without any misaligned comma character or any running disparity based code violation in between. in the event of any such code violation, the machine would reset itself to the ground state and start its search for the idle ordered sets again. in the synchronization achieved state, the machine constantly monitors the received data and looks for any kind of code violation that might result due to running disparity errors. if it were to receive four such consecu- tive invalid words, the link machine loses its synchroni- zation and once again enters the loss of synchronization state (los). a pair of valid words received by the machine overcomes the effect of a pre- viously encountered code violation. los is indicated by the status of wdsync output which now transitions from 1 to 0. at this point the machine attempts to estab- lish the link yet again. figure 6 shows the state diagram for the fibre-channel link state machine. 2266(f) figure 6. fibre-channel link state machine state diagram los = 1 os: idle ordered set (a 4 character based word having comma as the 1st character) vw rst link synchronization achieved (wdsync = 1) os cv os os os cv cv cv cv cv vw vw vw 2 vw 2 vw 2 vw a b c d e h g f loss of synchronization (wdsync = 0) lsm_enable + powerup reset vw: valid word (a 4 character based word having no code violation) cv: code violation (running disparity based on illegal comma position)
agere systems inc. 23 preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel backplane transceiver core detailed description (continued) xaui link synchronization function for each lane, the receive section of the xaui link state machine incorporates a synchronization state machine that monitors the status of the 10-bit alignment. a 10-bit alignment is done in the serdes based on a comma character such as k28.5. a comma (0011111 or its complement 1100000) is a unique pattern in the 10-bit space that cannot appear across the boundary between any two valid 10-bit code-groups. this property makes the comma useful for delimiting code-groups in a serial stream.this mechanism incorporates a hysteresis to prevent false synchronization and loss of synchronization due to infrequent bit errors. for each lane, the sync_complete signal is disabled until the lane achieves synchronization. the synchronization state diagram is shown in figure 1. table 1 and table 2 describe the state variables used in figure 1. table 5. xaui link synchronization state diagram notation ? variables table 6. xaui link synchronization state diagram ? functions variable description sync_status fail: lane is not synchronized (correct 10-bit alignment has not been estab- lished). ok: lane is synchronized. ok_noc: lane is synchronized but a comma character has not been detected in the past tbd seconds. enable_cdet true: align subsequent 10-bit words to the boundary indicated by the next received comma. false: maintain current 10-bit alignment. gd_cg current number of consecutive cg_good indications. function description sync_complete indication that alignment code-group alignment has been established at the boundary indicated by the most recently received comma. cg_comma indication that a valid code-group, with correct running disparity, containing a comma has been received. cg_good indication that a valid code-group with the correct running disparity has been received. cg_bad indication that an invalid code-group has been received. no_comma indication that comma timer has expired. the timer is initialized upon receipt of a comma.
24 agere systems inc. preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel backplane transceiver core detailed description (continued) 2273(f) figure 7. xaui link synchronization state diagram loss_of_sync sync_status <= fail enable_cdet <= true sync_complete reset comma_detect_1 enable_cdet <= false cg_bad cg_bad cg_comma cg_comma cg_bad comma_detect_2 comma_detect_3 cg_comma sync_aqc ? d_1 sync_aqc ? d_1a sync_status <= ok no_comma sync_status <= ok_noc cg_bad cg_bad cg_comma sync_aqc ? d_2 sync_aqc ? d_3 sync_aqc ? d_4 sync_aqc ? d_2a sync_aqc ? d_3a sync_aqc ? d_4a gd_cg <= gd_cg+1 gd_cg <= 0 cg_good cg_good* (gd_cg != 3) cg_bad cg_good*(gd_cg=3) cg_good* (gd_cg != 3) cg_bad cg_good*(gd_cg=3) cg_good cg_bad cg_good*(gd_cg=3) cg_good cg_good* (gd_cg != 3) cg_bad cg_bad cg_bad gd_cg <= 0 gd_cg <= 0 gd_cg <= gd_cg+1 gd_cg <= gd_cg+1
agere systems inc. 25 preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel backplane transceiver core detailed description (continued) mux/demux block transmit path (fpga backplane) the mux is responsible for taking 36 bits of data/con- trol at the low-speed transmit interface and up-convert- ing it to 9 bits of data/control at the serdes transmit interface. the mux has 2 clock domains: one based on a clock received from the serdes; the other that comes from the fpga at 1/4 the frequency of the serdes clock. the time sequence of interleaving data/control values is shown in figure 8 below. the low-speed transmit interface consists of a clock, 4 data byte values and a control bit for each of the byte values. the data bytes are conveyed to the mux via the twdx[31:0] ports. the control bits are tcom- max[3:0]. the clock is tsys_clk(a, b). both the data and control are strobed into the mux at this interface on the rising edge of tsys_clk(a, b). besides taking in a clock for capture, the interface sends back a clock of the same frequency, but arbitrary phase. this clock, tck78, is derived from one of the 4 channels of mux. within each mux is a divide-by-4 of the serdes tbcx311 clock used in synchronizing the transmit data words to the tbcx311 clock domain. tcksel[1:0] bits select the source channel of tck78. when tcksel[1:0] is 00, the clock source is channel a, 01 is channel b, 10 is channel c, and 11 is channel d. in many cases, this tck78 clock is used to drive the low-speed clock in the fpga that is connected to the tsys_clk(a, b) signal. 2267(f) figure 8. transmit mux block for a single serdes channel pll 8b/10b encoder 10 32 4 8 tsys_clk(a, b) tcommax[3:0] embedded core fpga data byte stbdx[7:0] k-control stbdx[8] 9 ground stbdx[9] stbc311x serdes mux pq r s t xyz stbdx[9:0] tcommax[3:0] latency = 4 tsys_clk (a, b) clocks twdx[31:0] parallel to serial (x 9) divide by 4 fifo mux 4 channels tcksel[1:0] tck78(a,b) twdx[31:0] tsys_clk (a, b) p 7-0 p 8 40-bit q 7-0 r 7-0 s 7-0 t 7-0 x 7-0 y 7-0 z 7-0 s 8 q 8 r 8 t 8 z 8 x 8 y 8 10-bit (the msb always tied to logic 0) block block
26 26 agere systems inc. preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel backplane transceiver core detailed description (continued) receive path (backplane fpga) the demux has to accumulate four sets of characters presented to it at the serdes receive interface and put these out at one time at the low-speed receive interface. another task of the demux is to recognize the synchro- nizing event and adjust the 4-byte boundary so that the synchronizing character leads off a new 4-byte word. this feature will be referred to as word alignment in other areas of this document. word alignment will only occur when the communication channel is synchro- nized. when there is no synchronization of the link, the demux will continue to output 4-byte words at some arbitrary, but constant, boundary. the demux passes on to the channel alignment fifo block a set of control signals that indicate the location of the synchronizing event. rcommax[3:0] are these indicators. if there is no link synchronization, all of the rcommax[3:0] bits will be 0s independent of synchro- nizing events that come in. when the link is synchro- nized, then the bit that corresponds to the time of the synchronization event will be set to a 1. the relationship between a time sequence of values input at srbdx[7:0] to the values output at rwdx[31:0] is shown in figure 9 below. a parallel relationship exists between srbdx[8] and rwbit8x[3:0] as well as between srbdx[9] and rwbit9x[3:0]. 2268(f) figure 9. receive demux block for a single serdes channel 8b/10b encoder pll & cdr 1:4 demux (x 10) xaui link srbdx[9:0] state sbytsyncx srbc0x scvx machine rwckx rcommax[3:0] rwbit8x[3:0] rwbit9x[3:0] serdes demux swdsyncx srbc1x pqrs t xyz srbdx[7:0] 10-bit rwdx[31:0] p 7-0 q 7-0 r 7-0 s 7-0 t 7-0 x 7-0 y 7-0 z 7-0 p 8 s 8 q 8 r 8 t 8 z 8 x 8 y 8 p 9 s 9 q 9 r 9 t 9 z 9 x 9 y 9 p c s c q c r c t c z c x c y c p q r s t x y z 40-bit rwdx[31:24] rwdx[23:16] rwdx[15:8] rwdx[7:0] block block latency = 4 rwckx clocks
agere systems inc. 27 preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel backplane transceiver core detailed description (continued) 5-8577 (f) figure 10. interconnect of streams for fifo alignment multichannel alignment (backplane fpga) the alignment fifo allows the transfer of all data to the system clock. the fifo sync block (figure 10) allows the system to be configured to allow the frame alignment of multiple slightly varying data streams. this optional alignment ensures that matching serdes streams will arrive at the fpga end in perfect data sync. the ort82g5 has a total of 8 channels (4 per ser- des). the incoming data of these channels can be synchronized in several ways, or they can be indepen- dent of one other. for example, all four channels in a serdes can be aligned together to form a communi- cation channel with a bandwidth of 10 gbits/s as shown in figure 11. optionally, the alignment can be extended across ser- des to align all 8 channels in ort82g5 as shown in figure 12. individual channels within an alignment group can be disabled (i.e., power down) without dis- rupting other channels. alternatively, two channels within a serdes can be aligned together; channel a and b and/or channel c and d can form a pair as shown in figure 13. 0673(f) figure 11. example of serdes a alignment and serdes b alignment 0674 figure 12. example of serdes a and b alignment 0675 figure 13. example of multiple twin channel alignment serdes a stream a serdes a stream b serdes a stream c serdes a stream d serdes b stream a serdes b stream b serdes b stream c fifo sync serdes b stream d serdes a serdes b serdes a stream a all 4 alignment of serdes a and serdes b t 0 t 1 serdes a stream b serdes a stream c serdes a stream d serdes b stream d serdes b stream c serdes b stream b serdes b stream a serdes b stream d serdes b stream c serdes b stream b serdes b stream a serdes a stream a serdes a stream b serdes a stream c serdes a stream d all 8 alignment of serdes a and serdes b t 0 serdes a stream a serdes a stream b serdes a stream c serdes a stream d serdes b stream d serdes b stream c serdes b stream b serdes b stream a serdes a stream a serdes a stream b serdes a stream c serdes a stream d serdes b stream d serdes b stream c serdes b stream b serdes b stream a two channel alignment t 1 t 2 serdes a stream a serdes a stream b serdes a stream c serdes a stream d serdes b stream d serdes b stream c serdes b stream b serdes b stream a t 0 serdes b stream d serdes b stream c serdes b stream b serdes b stream a serdes a stream a serdes a stream b serdes a stream c serdes a stream d twin alignment of stream a & b of serdes a twin alignment of stream c & d of serdes a twin alignment of stream c & d of serdes b
28 agere systems inc. preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel backplane transceiver core detailed description (continued) the multiplexed, receive word outputs to the fpga are shown in figure 14. these are each 40 bits wide. there are eight of these interfaces, one for each data lane. each consist of four 10-bit characters, or four decoded characters (each 8 bits + 1 bit k_ctrl) + ch248_syncx status indicator bit depending on setting of nochalgnx control register bits. note that there is one control bit for a bank of channels, for a total of two control bits. also, note that while 10 bits are provided for each character when nochalgnx = 1, only the lower 9 bits of each character will be meaningful if the 8b10br bit is configured to 1 for that serdes channel. with x representing the bank (placeholder for a or b) and y representing the channel (placeholder for a, b, c, or d) the 40-bit mrwdxy[39:0] is allocated as in table x. in the receive path, each channel is provided with a 24 word x 36-bit fifo. the fifo can perform two tasks: (1) to change the clock domain from receive clock to a clock from the fpga side, and (2) to align the receive data over 2, 4, or 8 channels. the input to the fifo consists of 36-bit demultiplexed data, rwbytesync[3:0], rwdx[31:0], and rwbit8x[3:0]. the four rwbytesync bits are control signals, e.g., they can be the commadet signals indicating the presence of comma character. the other 32 rwd bits are the 4 characters from the 8b/10b decoder. the rwbit8 indicates the presence of km.n control character in the receive data byte. only rwbit8 and rwd inputs are stored in the fifo. during alignment process, rwbytesync is used to synchronize multiple channels. if a channel is not in any alignment group, it will set the fifo-write-address to the beginning of the fifo, and will set the fifo-read- address to the middle of the fifo, at the first assertion of rwbytesync after reset or after the resync command. 2269(f) figure 14. multichannel alignment fifo block for a single serdes channel 1:4 demux (x 10) xaui link state machine rwckx rwbytesync[3:0] demux rwdx[31:0] 40 mrwdx rwckx fpga multi-channel alignment fifo 2:1 multiplexer (x 40) 40 36 channel align embedded core mux 4 channels rcksel[1:0] rck78(a,b) rsys_clk(a,b) (from global or secondary fpga clock networks) (to local fpga secondary clock network) (to global fpga system clock network)
agere systems inc. 29 preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel backplane transceiver core detailed description (continued) the use of the fifo is controlled by configuration bits, and the raw demultiplexed data can also be sent to the fpga directly, by passing the alignment fifo. the control register bits for alignment fifo in ort82g5 are described below. table 7. multichannel alignment modes where xx is one of a[a:d] and b[a:d]. to align all eight channels: fmpu_synmode_a[a:d] = 11 fmpu_synmode_b[a:d] = 11 to align all four channels in serdes a: fmpu_synmode_a[a:d] = 10 to align two channels in serdes a: fmpu_synmode_a[a:b] = 01 for channel aa and ab fmpu_synmode_a[c:d] = 01 for channel ac and ad similar alignment can be defined for serdes b. to enable/disable synchronization signal of individual channel within a multi-channel alignment group: fmpu_str_en_xx = 1 enabled fmpu_str_en_xx = 0 disabled where xx is one of a[a:d] and b[a:d]. to re-synchronize a multi-channel alignment group set the following bit to zero, and then set it to 1. fmpu_resync8 for eight channel a[a:d] and b[a:d] fmpu_resync4a for quad channel a[a:d] fmpu_resync2a1 for twin channel a[a:b] fmpu_resync2a2 for twin channel a[c:d] fmpu_resync4b for quad channel b[a:d] fmpu_resync2b1 for twin channel b[a:b] fmpu_resync2b2 for twin channel b[c:d] to resynchronize an independent channel (resetting the write and the read pointer of the fifo) set the fol- lowing bit to zero, and then set it to 1. fmpu_resync1_xx where xx is one of a[a:d] and b[a:d] a two-to-one multiplexor is used to select between aligned or nonaligned data to be sent to the fpga on mrwdxy[39:0]. with x representing the bank (place- holder for a or b) and y representing the channel (placeholder for a, b, c or d), the 40-bit mrwdxy[39:0] is allocated as shown in table 8. alignment sequence 1. follow steps 1 and 2 in the start up sequence described previously. 2. initiate a serdes software reset by setting the swrst bit to 1 and then to 0. note that, any changes to the serdes configuration bits should be followed by a software reset. 3. wait for 3 ms. refclk_[p, n] should be toggling by this time. during this time, configure the follow- ing registers. set the following bits in registers 30820, 30920 xaui_modex-set to 1 for xaui mode or keep the default value of 0. enable channel alignment by setting sync bits in registers 30811, 30911 fmpu_synmode_xx. set to appropriate val- ues for 2, 4, or 8 alignment. set rclkselx and tckselx bits in registers 30a00. rckselx-choose clock source for 78 mhz rck78x. tckselx-choose clock source for 78 mhz tck78x. 4. send data on serial links. monitor the following sta- tus/alarm bits: monitor the following alarm bits in registers 30000, 30010, 30020, 30030, 30100, 30110, 30120, 30130. lki-pll lock indicator. a 1 indicates that pll has achieved lock. sdon-signal detect output indicator. a 0 indi- cates active data. monitor the following status bits in registers 30804, 30904 xauistat_xx-in xaui mode, they should be 01 or 10. register bits fmpu_synmode_xx mode 00 no multichannel alignment. 01 twin channel alignment. 10 quad channel alignment. 11 eight channel alignment.
30 agere systems inc. preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel backplane transceiver core detailed description (continued) monitor the following status bits in registers 30805, 30905 demuxwas_xx-they should be 1 indicating word alignment is achieved. ch248_syncxx-they should be 1 indicating channel alignment. this is cleared by resync. 5. write a 1 to the appropriate resync registers 30820, 30920. note that this assumes that the previous value of the resync bits are 0. the resync operation requires a rising edge. two writes are required to the resync bits: write a 0 and then write a 1. check out-of-sync and fifo overflow status in registers 30814 (bank a). sync4_a_oos, sync4_a_ovfl-by 4 alignment. sync2_a2_oos, sync_a2_ovfl or sync2_a!_oos, sync2_a!_ovfl-by 2 alignment. check out-of-sync status in registers 30914 (bank 4). sync4_b_oos, sync4_b_ovfl-by 4 alignment. sync_b2_oos, sync2_b2_ovfl or sync2_b1_oos, sync_b1_ovfl-by 2 alignment. check out-of-sync status in register 30a03 sync8_oos, sync8_ovfl-by 8 alignment. if out-of-sync bit is 1 or fifo overflow is 1 then rewrite a 1 to the appropriate resync registers and monitor the oos and ovfl bits again. the resync operation requires a rising edge. two writes are required to the resync bits: write a 0 and then write a 1. alignment can also be done between the receive channels on two ort82g5 devices. each of the two devices needs to provide its aligned k_ctrl or other alignment character to the other device, which will delay reading from a second alignment fifo until all channels requesting alignment on the current device and all channels requesting alignment on the other device are aligned (as indicated on the k_ctrl character). this second alignment fifo will be implemented in fpga logic on the ort82g5. this scheme also requires that the refer- ence clock for both devices be driven by the same signal. xaui lane alignment function (lane deskew) in xaui mode, the receive section in each lane uses the /a/ code group to compensate for lane-to-lane skew. the mechanism restores the timing relationship between the 4 lanes by lining up the /a/ characters into a column. fig- ure 2 shows the alignment of four lanes based on /a/ character. a minimum spacing of 16 code-groups implies that at least 80 bits of skew compensation capability should be provided, which the ort82g5 significantly exceeds. 2392(f) figure 15. de-skew lanes by aligning /a/ columns lane 0 k rrkrk rkkrkrrk a lane 1 k rrkrk rkkrkrrk a lane 2 k rrkrk rkkrkrrk a lane 3 k rrkrk rkkrkrrk a lane 0 k rrkrk rkkrkrrk a lane 1 k rrkrk rkkrkrrk a lane 2 k rrkrk rkkrkrrk a lane 3 k rrkrk rkkrkrrk a
agere systems inc. 31 preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel backplane transceiver core detailed description (continued) table 8. definition of bits of mrwdxy[39:0] bit index nochalgnx = 1 nochalgnx = 0 39 b9 of char 1 ch248_syncx 38 b8 of char 1 k_ctrl for char 1 37 b7 of char 1 b7 of char 1 36 b6 of char 1 b6 of char 1 35 b5 of char 1 b5 of char 1 34 b4 of char 1 b4 of char 1 33 b3 of char 1 b3 of char 1 32 b2 of char 1 b2 of char 1 31 b1 of char 1 b1 of char 1 30 b0 of char 1 b0 of char 1 29 b9 of char 2 n/c 28 b8 of char 2 k_ctrl for char 2 27 b7 of char 2 b7 of char 2 26 b6 of char 2 b6 of char 2 25 b5 of char 2 b5 of char 2 24 b4 of char 2 b4 of char 2 23 b3 of char 2 b3 of char 2 22 b2 of char 2 b2 of char 2 21 b1 of char 2 b1 of char 2 20 b0 of char 2 b0 of char 2 19 b9 of char 3 n/c 18 b8 of char 3 k_ctrl for char 3 17 b7 of char 3 b7 of char 3 16 b6 of char 3 b6 of char 3 15 b5 of char 3 b5 of char 3 14 b4 of char 3 b4 of char 3 13 b3 of char 3 b3 of char 3 12 b2 of char 3 b2 of char 3 11 b1 of char 3 b1 of char 3 10 b0 of char 3 b0 of char 3 09 b9 of char 4 n/c 08 b8 of char 4 k_ctrl for char 4 07 b7 of char 4 b7 of char 4 06 b6 of char 4 b6 of char 4 05 b5 of char 4 b5 of char 4 04 b4 of char 4 b4 of char 4 03 b3 of char 4 b3 of char 4 02 b2 of char 4 b2 of char 4 01 b1 of char 4 b1 of char 4 00 b0 of char 4 b0 of char 4
32 agere systems inc. preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel backplane transceiver core detailed description (continued) loopback modes the device can be exercised in four possible loopback modes. these loopback modes are identified as: high-speed serial loopback parallel loopback at the serdes boundary parallel loopback at mux/demux boundary excluding serdes operational mode full loopback using the prbs generator/checker these four loopback modes are described next. high-speed serial loopback the high-speed serial loopback involves the transmit signal at the serial interface being looped back internally to the receive circuitry. the serial loopback path does not include the high-speed input and output buffers. the hdoutp, hdoutn outputs are active in this loopback mode, but the cml input buffers are powered down. the data are sourced at the ldin[9:0] pins and detected at the ldout[9:0] pins. the device is otherwise in its normal mode of operation. the data rate selection bits, txhr and rxhr, in the channel configuration registers must be configured to carry the same value and the prbs generator and checker are excluded by setting the prbs con- figuration bit to 0. the 8b/10b encoder/decoder can optionally be configured into or out of the loopback path. the following table 9 illustrates the control interface register configuration for the high-speed serial loopback. table 9. high-speed serial loopback configuration register address bit value bit name comments 30002, 30012, 30022, 30032, 30102, 30112, 30122, 30132 bit 0 = 0 or 1 txhr set to 0 or 1. txhr and rxhr bits must be set to the same value. 30002, 30012, 30022, 30032, 30102, 30112, 30122, 30132 bit 7 = 0 or 1 8b10bt set to 0 or 1. if set to 0, the 8b/10b encoder is excluded from the loopback path. the 8b/10b encoder and decoder selection control bits must both be set to the same value. 30003, 30013, 30023, 30033, 30103, 30113, 30123, 30133 bit 0 = 0 or 1 rxhr set to 0 or 1. txhr and rxhr bits must be set to the same value. 30003, 30013, 30023, 30033, 30103, 30113, 30123, 30133 bit 3 = 0 or 1 8b10br set to 0 or 1. if set to 0, the 8b/10b decoder is excluded from the loopback path. the 8b/10b encoder and decoder selection control bits must both be set to the same value. 30004, 30014, 30024, 30034, 30104, 30114, 30124, 30134 bit 0 = 0 prbs set to 0. 30004, 30014, 30024, 30034, 30104, 30114, 30124, 30134 bit 7 = 1 testen set to 1 if the loopback is done on a per-channel basis. however, if the loopback is done globally on all the four channels, this bit can be set to 0 but bit 7 of register 5 must be set to 1. 30005, 30105 bit 7 = 1 gtesten set to 1 if the loopback is done globally on all four channels. 30006, 30106 bits[4:0] = 00000 ? set to 00000.
agere systems inc. 33 preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel backplane transceiver core detailed description (continued) parallel loopback at the serdes boundary the parallel loopback involves the parallel buses ldin[9:0] and ldout[9:0]. the loopback connection is made such that ldin[9:0] is logically equivalent to ldout[9:0]. in the parallel loopback mode, the ldout[9:0] pins remain active. the receive data are sourced at the hdinp, hdinn pins and detected at the hdoutp, hdoutn pins. the device is otherwise in its normal mode of operation. the data rate selection bits txhr and rxhr in the channel configuration registers must be configured to carry the same value and the prbs generator and checker are excluded by setting the prbs configuration bit to 0. also, the 8b/10b encoder and decoder are excluded from the loopback path by setting the 8b10bt and 8b10br configuration bits to 0. table 10 illustrates the control inter- face register configuration for the parallel loopback. table 10. parallel loopback configuration parallel loopback at mux/demux boundary excluding serdes this is a low-frequency testmode. this parallel loopback involves the parallel buses srbdx[9:0] and stbdx[9:0]. the loopback connection is made such that srbdx[9:0] is logically equivalent to stbdx[9:0] and stbdx[9:0] remains active, thus bypassing the serdes. data can be sent from the fpga through twdxx signals and moni- tored on mrwdxx signals. this test is enabled by setting the pin ploop_test_enn to 1. pasb_testclk must be running in this mode at 4x frequency of rsys_clk[a, b] or tsys_clk[a, b]. register address bit value bit name comments 30002, 30012, 30022, 30032, 30102, 30112, 30122, 30132 bit 0 = 0 or 1 txhr set to 0 or 1. txhr and rxhr bits must be set to the same value. 30002, 30012, 30022, 30032, 30102, 30112, 30122, 30132 bit 7 = 0 8b10bt set to 0. the 8b/10b encoder is excluded from the loopback path. the 8b/10b encoder and decoder selection control bits must both be set to 0. 30003, 30013, 30023, 30033, 30103, 30113, 30123, 30133 bit 0 = 0 or 1 rxhr set to 0 or 1. txhr and rxhr bits must be set to the same value. 30003, 30013, 30023, 30033, 30103, 30113, 30123, 30133 bit 3 = 0 8b10br set to 0. the 8b/10b decoder is excluded from the loopback path. the 8b/10b encoder and decoder selection control bits must both be set to 0. 30004, 30014, 30024, 30034, 30104, 30114, 30124, 30134 bit 0 = 0 prbs set to 0. 30004, 30014, 30024, 30034, 30104, 30114, 30124, 30134 bit 7 = 1 ? set to 1 if the loopback is done on a per-channel basis. however, if the loopback is done globally on all the four channels, this bit can be set to 0 but bit 7 of regis- ter 5 must be set to 1. 30005, 30105 bit 7 = 1 ? set to 1 if the loopback is done globally on all four channels. 30006, 30106 bits[4:0] =00001 ? set to 00001.
34 agere systems inc. preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel backplane transceiver core detailed description (continued) operational mode full loopback test using the prbs generator/checker the operational mode full loopback test forms one of the normal operational modes of the device. the loopback can be either internal to the device or external to it. to perform the test with internal loopback, the loopenb pin should be set to a logic 1. the test includes the prbs generator in the transmit path and the prbs checker in the receive path. in this case, the device is placed in its normal operational mode with all the functional blocks in the transmit and the receive path active. the transmit data is generated by an lfsr. the generated word is then seri- alized and looped back (either internally or externally) to the receiver. the receiver first deserializes the 8-bit word to regenerate the transmitted 8-bit word. the prbs checker on the receiver compares the regenerated 8-bit word against the transmitted 8-bit word on a word by word basis and signals a mismatch by asserting a prbschk alarm status bit. during this test, the receiver regenerated 8-bit words can also be observed on the device output ports. the prbs checker contains a watchdog timer which asserts the time-out alarm status bit, prbstout, if the prbs test cannot progress beyond its start state within a reasonable time interval. this time interval is set by the precision of the watchdog timer. both the prbschk and the prbstout alarms can generate an interrupt if their corresponding masks are disabled. asb memory blocks this section describes the memory blocks in the embedded core. note that although the memory blocks are in the embedded core part of the chip, they do not interact with the rest of the embedded core circuits. they are stand- alone blocks designed specifically to increase ram capacity in the ort82g5 chip, and will be used by the soft ip cores in the fpga. there are two independent memory blocks in the embedded core. these are in addition to the block rams found in the fpga portion of the ort82g5. a block diagram of a memory block is shown in figure 16. each memory block has a capacity of 4k word by 36 bit. it has one read port and one write port and four byte-write-enable (active-low) signals. the read data from the memory block is registered so that it works as a pipelined synchronous memory block. a block diagram of the memory block in shown below in figure 16.the minimum timing specifications are shown in figure 18. 2270(f) figure 16. block diagram of memory block 4k x 36 memory block (1 of 2) d_x[35:0] ckw_x cswa_x cswb_x aw_x[10:0] bytewn_x[3] bytewn_x[2] bytewn_x[1] bytewn_x[0] bw[35,31:24] bw[34,23:16] bw[33,15:8] bw[32,7:0] ckr_x csr_x ar_x[10:0] q_x[35:0] write ports read ports
agere systems inc. 35 preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel backplane transceiver core detailed description (continued) 2271(f) figure 17. minimum timing specs for memory blocks-write cycle 2272(f) figure 18. minimum timing specs for memory blocks-read cycle csw[a,b] aw[10:0] ckw d[35:0] bytewn[3:0] 1.5 ns 2.0 ns 0.5 ns 0.3 ns 0.5 ns 0.3 ns 0.5 ns 0.3 ns 0.7 ns 0.3 ns ckr ar[10:0], csr q[35:0] 1.5 ns 1.5 ns 4.5 ns 0.5 ns 2.0 ns 0 ns
36 agere systems inc. preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel memory map definition of register types the registers in ort82g5 are 8-bit memory locations, which in general can be classified into the following types: status register and control register. status register read-only register to convey the status information of various operations within the fpsc core. an example is the state of the xaui link-state-machine. control register read-write register to set up the control inputs that define the operation of the fpsc core. the serdes block within the ort82g5 core has a set of status and control registers for it ? s operation. the detailed description of them can be found in the serdes data sheet. there is another group of status and control registers which are implemented outside the serdes, which are related to the serdes and other functional blocks in the fpsc core. they will be described in detail here. each serdes has four independent channels, which are named a, b, c, or d. using this nomenclature, the serdes a channels are named as aa, ab, ac, and ad, while serdes b channels will be ba, bb, bc, and bd. table 11. structural register elements a full memory map is included in table 12. address (hex) description 300xx serdes a, internal registers. 301xx serdes b, internal registers. 308xx channel a [a:d] registers (external to serdes blocks). 309xx channel b [a:d] registers (external to serdes blocks). 30a0x global registers (external to serdes blocks).
agere systems inc. 37 preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel memory map (continued) table 12 details the memory map for the asic core of the ort82g5 device. this table shows the databus oriented for the ppc interface. db0 is the msb, while db7 is the lsb. if the user master interface is used to preform opera- tions to the asic core then the databus must be used in the opposite notation, where db7 is the msb and db0 is the lsb. table 12. memory map addr (hex) reg # db0 db1 db2 db3 db4 db5 db6 db7 default value serdes a alarm registers (read only) 30000 sdon_aa receive signal detect output, bank a, channel a. when sdon_aa = 0, then active data is present. lki_aa receive pll lock indication, bank a, channel a. when lki_aa = 1, then pll receive is locked. prbschk_aa prbs check pass/ fail indication, bank a, channel a. when prbschk_aa = 0, then it is a pass indi- cation. prbstout_aa prbs checker watch- dog timer time-out alarm, bank a, channel a. when prbstout_aa = 1, then timeout has occurred. ???? 00 30010 sdon_ab receive signal detect output, bank a, channel b. when sdon_ab = 0, then active data is present. lki_ab receive pll lock indication, bank a, channel b. when lki_ab = 1, then pll receive is locked. prbschk_ab prbs check pass/ fail indication, bank a, channel b. when prbschk_ab = 0, then it is a pass indi- cation. prbstout_ab prbs checker watch- dog timer time-out alarm, bank a, channel b. when prbstout_ab = 1, then timeout has occurred. ???? 00 30020 sdon_ac receive signal detect output, bank a, channel c. when sdon_ac = 0, then active data is present. lki_ac receive pll lock indication, bank a, channel c. when lki_ac = 1, then pll receive is locked. prbschk_ac prbs check pass/ fail indication, bank a, channel c. when prbschk_ac = 0, then it is a pass indi- cation. prbstout_ac prbs checker watch- dog timer time-out alarm, bank a, channel c. when prbstout_ac = 1, then timeout has occurred. ???? 00 30030 sdon_ad receive signal detect output, bank a, channel d. when sdon_ad = 0, then active data is present. lki_ad receive pll lock indication, bank a, channel d. when lki_ad = 1, then pll receive is locked. prbschk_ad prbs check pass/ fail indication, bank a, channel d. when prbschk_ad = 0, then it is a pass indi- cation. prbstout_ad prbs checker watch- dog timer time-out alarm, bank a, channel d. when prbstout_ad = 1, then timeout has occurred. ???? 00 serdes a alarm mask registers 30001 msdon_aa mask receive sig- nal detect output, bank a, channel a. mlki_aa mask receive pll lock indication, bank a, channel a. mprbschk_aa. mask prbs check pass/fail indication, bank a, channel a. mprbstout_aa mask prbs checker watchdog timer time- out alarm, bank a, channel a. ???? ff 30011 msdon_ab mask receive sig- nal detect output, bank a, channel b. mlki_ab mask receive pll lock indication, bank a, channel b. mprbschk_ab. mask prbs check pass/fail indication, bank a, channel b. mprbstout_ab mask prbs checker watchdog timer time- out alarm, bank a, channel b. ???? ff 30021 msdon_ac mask receive sig- nal detect output, bank a, channel c. mlki_ac mask receive pll lock indication, bank a, channel c. mprbschk_ac. mask prbs check pass/fail indication, bank a, channel c. mprbstout_ac mask prbs checker watchdog timer time- out alarm, bank a, channel c. ???? ff 30031 msdon_ad mask receive sig- nal detect output, bank a, channel d. mlki_ad mask receive pll lock indication, bank a, channel d. mprbschk_ad. mask prbs check pass/fail indication, bank a, channel d. mprbstout_ad mask prbs checker watchdog timer time- out alarm, bank a, channel d. ???? ff
38 agere systems inc. preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel memory map (continued) table 12. memory map (continued) addr (hex) reg # db0 db1 db2 db3 db4 db5 db6 db7 default value serdes a transmit channel configuration registers 30002 txhr_aa transmit half rate selec- tion bit, bank a, channel a. when txhr = 1, the trans- mitter sam- ples data on the falling edge of the tbc clock. when txhr = 0, the trans- mitter sam- ples data on the falling edge of the double rate clock (derived from tbc). txhr = 0 on device reset. pwrdnt_aa transmit pow- erdown con- trol bit, bank a, channel a. when pwrdnt = 1, sections of the transmit hard- ware are pow- ered down to conserve power. pwrdnt = 0 on device reset. pe0_aa transmit pre- emphasis selection bit 0, bank a, channel a. pe0, together with pe1, selects one of three preem- phasis set- tings for the transmit sec- tion. pe0 = 0 on device reset. pe1_aa transmit pre- emphasis selection bit 1, bank a, channel a. pe1, together with pe0, selects one of three preem- phasis set- tings for the transmit sec- tion. pe1 = 0 on device reset. hamp_aa transmit half amplitude selection bit, bank a, chan- nel a. when hamp = 1, the transmit out- put buffer volt- age swing is limited to half its amplitude. otherwise, the transmit out- put buffer maintains its full voltage swing. hamp = 0 on device reset. tbcksel_aa transmit byte clock selec- tion bit, bank a, channel a. when tbck- sel = 0, the internal xck is selected. otherwise, the tbc clock is selected. tbcksel = 0 on device ser- set. ringovr_aa transmit ring counter bub- ble detector alarm over- ride control bit, bank a, channel a. when rin- govr = 0, the bubble detec- tor alarm is effective. oth- erwise, the bubble detec- tor alarm is not effective. rin- govr = 0 on device reset. 8b10bt_aa transmit 8b/ 10b encoder enable bit, bank a, chan- nel a. when 8b10bt = 1, the 8b/10b encoder on the transmit path is enabled. oth- erwise, it is bypassed. 8b10bt = 0 on device reset. 00 30012 txhr_ab transmit half rate selec- tion bit, bank a, channel b. when txhr = 1, the trans- mitter sam- ples data on the falling edge of the tbc clock. when txhr = 0, the trans- mitter sam- ples data on the falling edge of the double rate clock (derived from tbc). txhr = 0 on device reset. pwrdnt_ab transmit pow- erdown con- trol bit, bank a, channel b. when pwrdnt = 1, sections of the transmit hard- ware are pow- ered down to conserve power. pwrdnt = 0 on device reset. pe0_ab transmit pre- emphasis selection bit 0, bank a, channel b. pe0, together with pe1, selects one of three preem- phasis set- tings for the transmit sec- tion. pe0 = 0 on device reset. pe1_ab transmit pre- emphasis selection bit 1, bank a, channel b. pe1, together with pe0, selects one of three preem- phasis set- tings for the transmit sec- tion. pe1 = 0 on device reset. hamp_ab transmit half amplitude selection bit, bank a, chan- nel b. when hamp = 1, the transmit out- put buffer volt- age swing is limited to half its amplitude. otherwise, the transmit out- put buffer maintains its full voltage swing. hamp = 0 on device reset. tbcksel_ab transmit byte clock selec- tion bit, bank a, channel b. when tbck- sel = 0, the internal xck is selected. otherwise, the tbc clock is selected. tbcksel = 0 on device ser- set. ringovr_ab transmit ring counter bub- ble detector alarm over- ride control bit, bank a, channel b. when rin- govr = 0, the bubble detec- tor alarm is effective. oth- erwise, the bubble detec- tor alarm is not effective. rin- govr = 0 on device reset. 8b10bt_ab transmit 8b/ 10b encoder enable bit, bank a, chan- nel b. when 8b10bt = 1, the 8b/10b encoder on the transmit path is enabled. oth- erwise, it is bypassed. 8b10bt = 0 on device reset. 00 30022 txhr_ac transmit half rate selec- tion bit, bank a, channel c. when txhr = 1, the trans- mitter sam- ples data on the falling edge of the tbc clock. when txhr = 0, the trans- mitter sam- ples data on the falling edge of the double rate clock (derived from tbc). txhr = 0 on device reset. pwrdnt_ac transmit pow- erdown con- trol bit, bank a, channel c. when pwrdnt = 1, sections of the transmit hard- ware are pow- ered down to conserve power. pwrdnt = 0 on device reset. pe0_ac transmit pre- emphasis selection bit 0, bank a, channel c. pe0, together with pe1, selects one of three preem- phasis set- tings for the transmit sec- tion. pe0 = 0 on device reset. pe1_ac transmit pre- emphasis selection bit 1, bank a, channel c. pe1, together with pe0, selects one of three preem- phasis set- tings for the transmit sec- tion. pe1 = 0 on device reset. hamp_ac transmit half amplitude selection bit, bank a, chan- nel c. when hamp = 1, the transmit out- put buffer volt- age swing is limited to half its amplitude. otherwise, the transmit out- put buffer maintains its full voltage swing. hamp = 0 on device reset. tbcksel_ac transmit byte clock selec- tion bit, bank a, channel c. when tbck- sel = 0, the internal xck is selected. otherwise, the tbc clock is selected. tbcksel = 0 on device ser- set. ringovr_ac transmit ring counter bub- ble detector alarm over- ride control bit, bank a, channel c. when rin- govr = 0, the bubble detec- tor alarm is effective. oth- erwise, the bubble detec- tor alarm is not effective. rin- govr = 0 on device reset. 8b10bt_ac transmit 8b/ 10b encoder enable bit, bank a, chan- nel c. when 8b10bt = 1, the 8b/10b encoder on the transmit path is enabled. oth- erwise, it is bypassed. 8b10bt = 0 on device reset. 00
agere systems inc. 39 preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel memory map (continued) table 12. memory map (continued) addr (hex) reg # db0 db1 db2 db3 db4 db5 db6 db7 default value serdes a transmit channel configuration registers (continued) 30032 txhr_ad transmit half rate selec- tion bit, bank a, channel d. when txhr = 1, the transmit- ter samples data on the falling edge of the tbc clock. when txhr = 0, the transmit- ter samples data on the falling edge of the double rate clock (derived from tbc). txhr = 0 on device reset. pwrdnt_a d transmit powerdown control bit, bank a, channel d. when pwrdnt = 1, sections of the transmit hardware are powered down to con- serve power. pwrdnt = 0 on device reset. pe0_ad transmit pre- emphasis selection bit 0, bank a, channel d. pe0, together with pe1, selects one of three preemphasis settings for the transmit section. pe0 = 0 on device reset. pe1_ad transmit pre- emphasis selection bit 1, bank a, channel d. pe1, together with pe0, selects one of three preemphasis settings for the transmit section. pe1 = 0 on device reset. hamp_ad transmit half amplitude selection bit, bank a, channel d. when hamp = 1, the transmit out- put buffer voltage swing is limited to half its ampli- tude. other- wise, the transmit out- put buffer maintains its full voltage swing. hamp = 0 on device reset. tbcksel_a d transmit byte clock selec- tion bit, bank a, channel d. when tbcksel = 0, the internal xck is selected. otherwise, the tbc clock is selected. tbcksel = 0 on device reset. ringovr_a d transmit ring counter bub- ble detector alarm over- ride control bit, bank a, channel d. when rin- govr = 0, the bubble detector alarm is effective. otherwise, the bubble detector alarm is not effective. ringovr = 0 on device reset. 8b10bt_ad transmit 8b/ 10b encoder enable bit, bank a, channel d. when 8b10bt = 1, the 8b/10b encoder on the transmit path is enabled. oth- erwise, it is bypassed. 8b10bt = 0 on device reset. 00
40 agere systems inc. preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel memory map (continued) table 12. memory map (continued) addr (hex) reg # db0 db1 db2 db3 db4 db5 db6 db7 default value serdes a receive channel configuration registers 30003 rxhr_aa receive half rate selection bit, bank a, channel a. when rxhr = 1, the rbc[1:0] clocks are issued at half the scheduled rate of the reference clock. rxhr = 0 on device reset. pwrdnr_aa receiver power down control bit, bank a, channel a. when pwrdnr = 1, sections of the receive hardware are powered down to conserve power. pwrdnr = 0 on device reset. sdovride_aa receive signal detect alarm over- ride bit, bank a, channel a. when sdovride = 1, the energy detector out- put from the receiver is masked. thus, when there is no receive data, the powerdown function is disabled and the corresponding sdon alarm is sup- pressed. sdovride = 1 on device reset. 8b10br_aa receive 8b/10b decoder enable bit, bank a, channel a. when 8b10br = 1, the 8b/10b decoder on the receive path is enabled. other- wise, it is bypassed. 8b10br = on device reset. linksm_aa link state machine enable bit, bank a, channel a. when linksm = 1, the receiver link state machine is enabled. otherwise, the link state machine is dis- ables. linksm = 0 on device reset. ??? 04 30013 rxhr_ab receive half rate selection bit, bank a, channel b. when rxhr = 1, the rbc[1:0] clocks are issued at half the scheduled rate of the reference clock. rxhr = 0 on device reset. pwrdnr_ab receiver power down control bit, bank a, channel b. when pwrdnr = 1, sections of the receive hardware are powered down to conserve power. pwrdnr = 0 on device reset. sdovride_ab receive signal detect alarm over- ride bit, bank a, channel b. when sdovride = 1, the energy detector out- put from the receiver is masked. thus, when there is no receive data, the powerdown function is disabled and the corresponding sdon alarm is sup- pressed. sdovride = 1 on device reset. 8b10br_ab receive 8b/10b decoder enable bit, bank a, channel b. when 8b10br = 1, the 8b/10b decoder on the receive path is enabled. other- wise, it is bypassed. 8b10br = on device reset. linksm_ab link state machine enalbe bit, bank a, channel b. when linksm = 1, the receiver link state machine is enabled. otherwise, the link state machine is dis- ables. linksm = 0 on device reset. ??? 04 30023 rxhr_ac receive half rate selection bit, bank a, channel c. when rxhr = 1, the rbc[1:0] clocks are issued at half the scheduled rate of the reference clock. rxhr = 0 on device reset. pwrdnr_ac receiver power down control bit, bank a, channel c. when pwrdnr = 1, sections of the receive hardware are powered down to conserve power. pwrdnr = 0 on device reset. sdovride_ac receive signal detect alarm over- ride bit, bank a, channel c. when sdovride = 1, the energy detector out- put from the receiver is masked. thus, when there is no receive data, the powerdown function is disabled and the corresponding sdon alarm is sup- pressed. sdovride = 1 on device reset. 8b10br_ac receive 8b/10b decoder enable bit, bank a, channel c. when 8b10br = 1, the 8b/10b decoder on the receive path is enabled. other- wise, it is bypassed. 8b10br = on device reset. linksm_ac link state machine enalbe bit, bank a, channel c. when linksm = 1, the receiver link state machine is enabled. otherwise, the link state machine is dis- ables. linksm = 0 on device reset. ??? 04 30033 rxhr_ad receive half rate selection bit, bank a, channel d. when rxhr = 1, the rbc[1:0] clocks are issued at half the scheduled rate of the reference clock. rxhr = 0 on device reset. pwrdnr_ad receiver power down control bit, bank a, channel d. when pwrdnr = 1, sections of the receive hardware are powered down to conserve power. pwrdnr = 0 on device reset. sdovride_ad receive signal detect alarm over- ride bit, bank a, channel d. when sdovride = 1, the energy detector out- put from the receiver is masked. thus, when there is no receive data, the powerdown function is disabled and the corresponding sdon alarm is sup- pressed. sdovride = 1 on device reset. 8b10br_ad receive 8b/10b decoder enable bit, bank a, channel d. when 8b10br = 1, the 8b/10b decoder on the receive path is enabled. other- wise, it is bypassed. 8b10br = on device reset. linksm_ad link state machine enalbe bit, bank a, channel d. when linksm = 1, the receiver link state machine is enabled. otherwise, the link state machine is dis- ables. linksm = 0 on device reset. ??? 04
agere systems inc. 41 preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel memory map (continued) table 12. memory map (continued) addr (hex) reg # db0 db1 db2 db3 db4 db5 db6 db7 default value serdes a common transmit and receive channel configuration registers 30004 prbs_aa transmit and receive prbs enable bit, bank a, channel a. when prbs = 1, the prbs generator on the transmitter and the prbs checker on the receiver are enabled. prbs = 0 on device reset. mask_aa transmit and receive alarm mask bit, bank a, channel a. when mask = 1, the trans- mit and receive alarms of a channel are prevented from generating an inter- rupt. this mask bit overrides the individ- ual alarm mask bits in the alarm mask reg- isters. mask = 1 on device reset. swrst_aa transmit and receive software reset bit, bank a, channel a. when swrst = 1, this bit provides the same function as the hardware reset, except all configura- tion register settings are preserved. this is not a self-clearing bit. once set, this bit must be cleared by writing a 0 to it. swrst = 0 on device reset. ???? testen_aa transmit and receive test enable bit, bank a, channel a. when testen = 1, the transmit and receive sections are placed in test mode. testen = 0 on device reset. when the global test enable bit gtesten = 0, the indi- vidual channel test enable bits are used to selectively place a channel in test or normal mode. when gtes- ten = 1, all channels are set to test mode regardless of their testen setting. 02 30014 prbs_ab transmit and receive prbs enable bit, bank a, channel b. when prbs = 1, the prbs generator on the transmitter and the prbs checker on the receiver are enabled. prbs = 0 on device reset. mask_ab transmit and receive alarm mask bit, bank a, channel b. when mask = 1, the trans- mit and receive alarms of a channel are prevented from generating an inter- rupt. this mask bit overrides the individ- ual alarm mask bits in the alarm mask reg- isters. mask = 1 on device reset. swrst_ab transmit and receive software reset bit, bank a, channel b. when swrst = 1, this bit provides the same function as the hardware reset, except all configura- tion register settings are preserved. this is not a self-clearing bit. once set, this bit must be cleared by writing a 0 to it. swrst = 0 on device reset. ???? testen_ab transmit and receive test enable bit, bank a, channel b. when testen = 1, the transmit and receive sections are placed in test mode. testen = 0 on device reset. when the global test enable bit gtesten = 0, the indi- vidual channel test enable bits are used to selectively place a channel in test or normal mode. when gtes- ten = 1, all channels are set to test mode regardless of their testen setting. 02 30024 prbs_ac transmit and receive prbs enable bit, bank a, channel c. when prbs = 1, the prbs generator on the transmitter and the prbs checker on the receiver are enabled. prbs = 0 on device reset. mask_ac transmit and receive alarm mask bit, bank a, channel c. when mask = 1, the trans- mit and receive alarms of a channel are prevented from generating an inter- rupt. this mask bit overrides the individ- ual alarm mask bits in the alarm mask reg- isters. mask = 1 on device reset. swrst_ac transmit and receive software reset bit, bank a, channel c. when swrst = 1, this bit provides the same function as the hardware reset, except all configura- tion register settings are preserved. this is not a self-clearing bit. once set, this bit must be cleared by writing a 0 to it. swrst = 0 on device reset. ???? testen_ac transmit and receive test enable bit, bank a, channel c. when testen = 1, the transmit and receive sections are placed in test mode. testen = 0 on device reset. when the global test enable bit gtesten = 0, the indi- vidual channel test enable bits are used to selectively place a channel in test or normal mode. when gtes- ten = 1, all channels are set to test mode regardless of their testen setting. 02 30034 prbs_ad transmit and receive prbs enable bit, bank a, channel d. when prbs = 1, the prbs generator on the transmitter and the prbs checker on the receiver are enabled. prbs = 0 on device reset. mask_ad transmit and receive alarm mask bit, bank a, channel d. when mask = 1, the trans- mit and receive alarms of a channel are prevented from generating an inter- rupt. this mask bit overrides the individ- ual alarm mask bits in the alarm mask reg- isters. mask = 1 on device reset. swrst_ad transmit and receive software reset bit, bank a, channel d. when swrst = 1, this bit provides the same function as the hardware reset, except all configura- tion register settings are preserved. this is not a self-clearing bit. once set, this bit must be cleared by writing a 0 to it. swrst = 0 on device reset. ???? testen_ad transmit and receive test enable bit, bank a, channel d. when testen = 1, the transmit and receive sections are placed in test mode. testen = 0 on device reset. when the global test enable bit gtesten = 0, the indi- vidual channel test enable bits are used to selectively place a channel in test or normal mode. when gtes- ten = 1, all channels are set to test mode regardless of their testen setting. 02
42 agere systems inc. preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel memory map (continued) table 12. memory map (continued) addr (hex) reg # db0 db1 db2 db3 db4 db5 db6 db7 default value serdes a global control register (acts on channels a, b, c, and d) 30005 gprbs_a global enable. the gprbs bit globally enables the prbs gen- erators and checkers all four channels of serdes a when gprbs = 1. gprbs = 0 on device reset. gmask_a global mask. the gmask globally masks all the channel alarms of ser- des a when gmask = 1. this prevents all the transmit and receive alarms from generat- ing an interrupt. gmask = 1 on device reset. gswrst_a reset func- tion. the gswrst bit provides the same function as the hardware reset for the transmit and receive sec- tions of all four channels of aserdes a, except that the device configu- ration settings are not affected when gswrst is asserted. gswrst = 0 on device reset. this is not a self-clearing bit. once set, it must be cleared by writing a 0 to it. gpwrdnt_a powerdown transmit func- tion. when gpwrdnt = 1, sections of the transmit hard- ware for all four channels of serdes a are powered down to conserve power. gpwrdnt = 0 on device reset. gpwrdnr_a powerdown receive func- tion. when gpwrdnr = 1, sections of the receive hardware for all four channels of serdes a are powered down to conserve power. gpwrdnr = 0 on device reset. gtristn_ a active-low tristn function. when gtristn = 0, the cmos out- put buffers for ser- des a are 3-stated. gtristn = 1 on device reset. ? gtesten_a test enable control. when gtesten = 1, the transmit and receive sections of all four channels of serdes a are placed in test mode. gtesten = 0 on device reset. 022
agere systems inc. 43 preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel memory map (continued) table 12. memory map (continued) addr (hex) reg # db0 db1 db2 db3 db4 db5 db6 db7 default value control registers a 30800 a0 enbysync_ aa byte align- ments bank a, channel a enbysync_ ab byte align- ments bank a, channel b enbysync_ ac byte alignments bank a, chan- nel c enbysync_ ad byte align- ments bank a, channel d lckrefn_a a lock receiver to ref. clock for bank a channel a lckrefn_a b lock receiver to ref. clock for bank a channel b lckrefn_a c lock receiver to ref. clock for bank a channel c lckrefn_a d lock receiver to ref. clock for bank a channel d 00 30801 a1 loopenb_a a enable loop- back mode for bank a, chan- nel a loopenb_a b enable loop- back mode for bank a, chan- nel b loopenb_a c enable loop- back mode for bank a, chan- nel c loopenb_a d enable loop- back mode for bank a, chan- nel d nowdalign _aa defeats demux align- ment for bank a, channel a nowdalign _ab defeats demux align- ment for bank a, channel b nowdalign _ac defeats demux align- ment for bank a, channel c nowdalign _ad defeats demux align- ment for bank a, channel 00 30802 a2 reserved for future use 30803 a3 reserved for future use 30810 a4 dowdalign _aa force new demux word alignment for bank a, chan- nel a dowdalign _ab force new demux word alignment for bank a, chan- nel b dowdalign _ac force new demux word alignment for bank a, chan- nel c dowdalign _ad force new demux word alignment for bank a, chan- nel d fmpu_str_ en _aa enable align- ment function for channel aa fmpu_str_ en _ab enable align- ment function for channel ab fmpu_str_ en_ac enable align- ment function for channel ac fmpu_str_ en_ad enable align- ment function for channel ad 00 30811 a5 fmpu_synmode_aa sync mode for aa fmpu_synmode_ab sync mode for ab fmpu_synmode_ac sync mode for ac fmpu_synmode_ad sync mode for ad 00 30812 a6 reserved for future use 30813 a7 reserved for future use 30820 a8 fmpu_resy nc1_aa resync a sin- gle channel, aa. write a 0, then write a 1. fmpu_resy nc1_ab resync a sin- gle channel, ab. write a 0, then write a 1. fmpu_resy nc1_ac resync a sin- gle channel, ac. write a 0, then write a 1. fmpu_resy nc1_ad resync a sin- gle channel, ad. write a 0, then write a 1. fmpu_resy nc2_a1 resync 2 channels, aa and ab. write a 0, then write a 1. fmpu_resy nc2a2 resync 2 channels, ac and ad. write a 0, then write a 1. fmpu_resy nc4a resync 4 channels a[a:d]. write a 0, then write a 1. xaui_mode a controls use of xaui link state machine vs. serdes link state machine for bank a 00 30821 a9 nochalgn a bypass chan- nel alignment demuxed data directly to fpga for bank a reserved for future use 00 30822 a10 reserved for future use 30823 a11 reserved for future use 30830 a12 reserved for future use 30831 a13 reserved for future use 30832 a14 reserved for future use 30833 a15 reserved for future use
44 agere systems inc. preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel memory map (continued) table 12. memory map (continued) * for xauistat_ay (address 0x30804), the definitions of these bits are: 00 ? no synchronization. 01 ? synchronization done. 10 ? synchronization done no comma has been detected. 11 ? not used. addr (hex) reg # db0 db1 db2 db3 db4 db5 db6 db7 default value status registers a 30804 a16 xauistat_aa* status of xaui link state machine for bank a, channel a xauistat_ab* status of xaui link state machine for bank a, channel b xauistat_ac* status of xaui link state machine for bank a, channel c xauistat_ad* status of xaui link state machine for bank a, channel d 00 30805 a17 demuxwas_ aa status of demux word alignment for bank a, chan- nel a demuxwas_ ab status of demux word alignment for bank a, chan- nel b demuxwas_ ac status of demux word alignment for bank a, chan- nel c demuxwas _ad status of demux word alignment for bank a, chan- nel d ch248_sync _aa alignment completed for aa ch248_sync _ab alignment completed for ab ch248_sync _ac alignment completed for ac ch248_sync _ad alignment completed for ad 00 30806 a18 reserved for future use 30807 a19 reserved for future use 30814 a20 sync2_a1 ovfl alignment fifo overflow aa and ab sync2_a2 ovfl alignment fifo overflow ac and ad sync4_a ovfl alignment fifo overflow for a[a:d] sync2_a1 oos alignment out of sync for aa and ab sync2_a2 oos alignment out of sync for ac and ad sync4_a_o os alignment out of sync for a[a:d] reserved for future use 30815 a21 reserved for future use 30816 a22 reserved for future use 30817 a23 reserved for future use 30824 a24 reserved for future use 30825 a25 reserved for future use 30826 a26 reserved for future use 30827 a27 reserved for future use 30834 a28 reserved for future use 30835 a29 reserved for future use 30836 a30 reserved for future use 30837 a31 reserved for future use
agere systems inc. 45 preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel memory map (continued) table 12. memory map (continued) addr (hex) reg # db0 db1 db2 db3 db4 db5 db6 db7 default value serdes b alarm registers (read only) 30100 sdon_ba receive signal detect output, bank b, channel a. when sdon_ba = 0, then active data is present. lki_ba receive pll lock indica- tion, bank b, channel a. when lki_ba = 1, then pll receive is locked. prbschk_ba prbs check pass/fail indica- tion, bank b, channel a. when prbschk_ba = 0, then it is a pass indica- tion. prbstout_ba prbs checker watch- dog timer time-out alarm, bank b, channel a. when prbstout_ba = 1, then timeout has occurred. ???? 00 30110 sdon_bb receive signal detect output, bank b, channel b. when sdon_bb = 0, then active data is present. lki_bb receive pll lock indica- tion, bank b, channel b. when lki_bb = 1, then pll receive is locked. prbschk_bb prbs check pass/fail indica- tion, bank b, channel b. when prbschk_bb = 0, then it is a pass indica- tion. prbstout_bb prbs checker watch- dog timer time-out alarm, bank b, channel b. when prbstout_bb = 1, then timeout has occurred. ???? 00 30120 sdon_bc receive signal detect output, bank b, channel c. when sdon_bc = 0, then active data is present. lki_bc receive pll lock indica- tion, bank b, channel c. when lki_bc = 1, then pll receive is locked. prbschk_bc prbs check pass/fail indica- tion, bank b, channel c. when prbschk_bc = 0, then it is a pass indica- tion. prbstout_bc prbs checker watch- dog timer time-out alarm, bank b, channel c. when prbstout_bc = 1, then timeout has occurred. ???? 00 30130 sdon_bd receive signal detect output, bank b, channel d. when sdon_bd = 0, then active data is present. lki_bd receive pll lock indica- tion, bank b, channel d. when lki_bd = 1, then pll receive is locked. prbschk_bd prbs check pass/fail indica- tion, bank b, channel d. when prbschk_bd = 0, then it is a pass indica- tion. prbstout_bd prbs checker watch- dog timer time-out alarm, bank b, channel d. when prbstout_bd = 1, then timeout has occurred. ???? 00 serdes b alarm mask registers 30101 msdon_ba mask receive signal detect output, bank b, channel a. mlki_ba mask receive pll lock indication, bank b, chan- nel a. mprbschk_ba. mask prbs check pass/fail indication, bank b, chan- nel a. mprbstout_ba mask prbs checker watchdog timer time- out alarm, bank b, channel a. ???? ff 30111 msdon_bb mask receive signal detect output, bank b, channel b. mlki_bb mask receive pll lock indication, bank b, chan- nel b. mprbschk_bb. mask prbs check pass/fail indication, bank b, chan- nel b. mprbstout_bb mask prbs checker watchdog timer time- out alarm, bank b, channel b. ???? ff 30121 msdon_bc mask receive signal detect output, bank b, channel c. mlki_bc mask receive pll lock indication, bank b, chan- nel c. mprbschk_bc. mask prbs check pass/fail indication, bank b, chan- nel c. mprbstout_bc mask prbs checker watchdog timer time- out alarm, bank b, channel c. ???? ff 30131 msdon_bd mask receive signal detect output, bank b, channel d. mlki_bd mask receive pll lock indication, bank b, chan- nel d. mprbschk_bd. mask prbs check pass/fail indication, bank b, chan- nel d. mprbstout_bd mask prbs checker watchdog timer time- out alarm, bank b, channel d. ???? ff
46 agere systems inc. preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel memory map (continued) table 12. memory map (continued) addr (hex) reg # db0 db1 db2 db3 db4 db5 db6 db7 default value serdes b transmit channel configuration registers 30102 txhr_ba transmit half rate selection bit, bank b, channel a. when txhr = 1, the transmit- ter samples data on the falling edge of the tbc clock. when txhr = 0, the transmitter sam- ples data on the falling edge of the double rate clock (derived from tbc). txhr = 0 on device reset. pwrdnt_ba transmit power- down control bit, bank b, channel a. when pwrdnt = 1, sections of the transmit hardware are powered down to conserve power. pwrdnt = 0 on device reset. pe0_ba transmit preem- phasis selec- tion bit 0, bank b, channel a. pe0, together with pe1, selects one of three preempha- sis settings for the transmit sec- tion. pe0 = 0 on device reset. pe1_ba transmit preem- phasis selec- tion bit 1, bank b, channel a. pe1, together with pe0, selects one of three preempha- sis settings for the transmit sec- tion. pe1 = 0 on device reset. hamp_ba transmit half amplitude selection bit, bank b, chan- nel a. when hamp = 1, the transmit output buffer voltage swing is limited to half its ampli- tude. other- wise, the transmit output buffer maintains its full voltage swing. hamp = 0 on device reset. tbcksel_ba transmit byte clock selection bit, bank b, channel a. when tbck- sel = 0, the internal xck is selected. other- wise, the tbc clock is selected. tbck- sel = 0 on device reset. ringovr_ba transmit ring counter bubble detector alarm override con- trol bit, bank b, channel a. when rin- govr = 0, the bubble detector alarm is effec- tive. otherwise, the bubble detector alarm is not effective. ringovr = 0 on device reset. 8b10bt_ba transmit 8b/10b encoder enable bit, bank b, channel a. when 8b10bt = 1, the 8b/10b encoder on the transmit path is enabled. other- wise, it is bypassed. 8b10bt = 0 on device reset. 00 30112 txhr_bb transmit half rate selection bit, bank b, channel b. when txhr = 1, the transmit- ter samples data on the falling edge of the tbc clock. when txhr = 0, the transmitter sam- ples data on the falling edge of the double rate clock (derived from tbc). txhr = 0 on device reset. pwrdnt_bb transmit power- down control bit, bank b, channel b. when pwrdnt = 1, sections of the transmit hardware are powered down to conserve power. pwrdnt = 0 on device reset. pe0_bb transmit preem- phasis selec- tion bit 0, bank b, channel b. pe0, together with pe1, selects one of three preempha- sis settings for the transmit sec- tion. pe0 = 0 on device reset. pe1_bb transmit preem- phasis selec- tion bit 1, bank b, channel b. pe1, together with pe0, selects one of three preempha- sis settings for the transmit sec- tion. pe1 = 0 on device reset. hamp_bb transmit half amplitude selection bit, bank b, chan- nel b. when hamp = 1, the transmit output buffer voltage swing is limited to half its ampli- tude. other- wise, the transmit output buffer maintains its full voltage swing. hamp = 0 on device reset. tbcksel_bb transmit byte clock selection bit, bank b, channel b. when tbck- sel = 0, the internal xck is selected. other- wise, the tbc clock is selected. tbck- sel = 0 on device reset. ringovr_bb transmit ring counter bubble detector alarm override con- trol bit, bank b, channel b. when rin- govr = 0, the bubble detector alarm is effec- tive. otherwise, the bubble detector alarm is not effective. ringovr = 0 on device reset. 8b10bt_bb transmit 8b/10b encoder enable bit, bank b, channel b. when 8b10bt = 1, the 8b/10b encoder on the transmit path is enabled. other- wise, it is bypassed. 8b10bt = 0 on device reset. 00 30122 txhr_bc transmit half rate selection bit, bank b, channel c. when txhr = 1, the transmit- ter samples data on the falling edge of the tbc clock. when txhr = 0, the transmitter sam- ples data on the falling edge of the double rate clock (derived from tbc). txhr = 0 on device reset. pwrdnt_bc transmit power- down control bit, bank b, channel c. when pwrdnt = 1, sections of the transmit hardware are powered down to conserve power. pwrdnt = 0 on device reset. pe0_bc transmit preem- phasis selec- tion bit 0, bank b, channel c. pe0, together with pe1, selects one of three preempha- sis settings for the transmit sec- tion. pe0 = 0 on device reset. pe1_bc transmit preem- phasis selec- tion bit 1, bank b, channel c. pe1, together with pe0, selects one of three preempha- sis settings for the transmit sec- tion. pe1 = 0 on device reset. hamp_bc transmit half amplitude selection bit, bank b, chan- nel c. when hamp = 1, the transmit output buffer voltage swing is limited to half its ampli- tude. other- wise, the transmit output buffer maintains its full voltage swing. hamp = 0 on device reset. tbcksel_bc transmit byte clock selection bit, bank b, channel c. when tbck- sel = 0, the internal xck is selected. other- wise, the tbc clock is selected. tbck- sel = 0 on device reset. ringovr_bc transmit ring counter bubble detector alarm override con- trol bit, bank b, channel c. when rin- govr = 0, the bubble detector alarm is effec- tive. otherwise, the bubble detector alarm is not effective. ringovr = 0 on device reset. 8b10bt_bc transmit 8b/10b encoder enable bit, bank b, channel c. when 8b10bt = 1, the 8b/10b encoder on the transmit path is enabled. other- wise, it is bypassed. 8b10bt = 0 on device reset. 00
agere systems inc. 47 preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel memory map (continued) table 12. memory map (continued) addr (hex) reg # db0 db1 db2 db3 db4 db5 db6 db7 default value serdes b transmit channel configuration registers (continued) 30132 txhr_bd transmit half rate selection bit, bank b, channel d. when txhr = 1, the transmit- ter samples data on the falling edge of the tbc clock. when txhr = 0, the transmitter sam- ples data on the falling edge of the double rate clock (derived from tbc). txhr = 0 on device reset. pwrdnt_bd transmit power- down control bit, bank b, channel d. when pwrdnt = 1, sections of the transmit hardware are powered down to conserve power. pwrdnt = 0 on device reset. pe0_bd transmit preem- phasis selec- tion bit 0, bank b, channel d. pe0, together with pe1, selects one of three preem- phasis settings for the transmit section. pe0 = 0 on device reset. pe1_bd transmit preem- phasis selec- tion bit 1, bank b, channel d. pe1, together with pe0, selects one of three preem- phasis settings for the transmit section. pe1 = 0 on device reset. hamp_bd transmit half amplitude selection bit, bank b, chan- nel d. when hamp = 1, the transmit output buffer voltage swing is limited to half its ampli- tude. other- wise, the transmit output buffer maintains its full voltage swing. hamp = 0 on device reset. tbcksel_bd transmit byte clock selection bit, bank b, channel d. when tbck- sel = 0, the internal xck is selected. other- wise, the tbc clock is selected. tbck- sel = 0 on device reset. ringovr_bd transmit ring counter bubble detector alarm override con- trol bit, bank b, channel d. when rin- govr = 0, the bubble detector alarm is effec- tive. otherwise, the bubble detector alarm is not effective. ringovr = 0 on device reset. 8b10bt_bd transmit 8b/10b encoder enable bit, bank b, channel d. when 8b10bt = 1, the 8b/10b encoder on the transmit path is enabled. other- wise, it is bypassed. 8b10bt = 0 on device reset. 00
48 agere systems inc. preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel memory map (continued) table 12. memory map (continued) addr (hex) reg # db0 db1 db2 db3 db4 db5 db6 db7 default value serdes b receive channel configuration registers 30103 rxhr_ba receive half rate selection bit, bank b, channel a. when rxhr = 1, the rbc[1:0] clocks are issued at half the scheduled rate of the reference clock. rxhr = 0 on device reset. pwrdnr_ba receiver power down control bit, bank b, channel a. when pwrdnr = 1, sections of the receive hardware are powered down to conserve power. pwrdnr = 0 on device reset. sdovride_ba receive signal detect alarm over- ride bit, bank b, channel a. when sdovride = 1, the energy detector out- put from the receiver is masked. thus, when there is no receive data, the powerdown function is disabled and the corresponding sdon alarm is suppressed. sdovride = 1 on device reset. 8b10br_ba receive 8b/10b decoder enable bit, bank b, channel a. when 8b10br = 1, the 8b/10b decoder on the receive path is enabled. otherwise, it is bypassed. 8b10br = on device reset. linksm_ba link state machine enalbe bit, bank b, channel a. when linksm = 1, the receiver link state machine is enabled. otherwise, the link state machine is dis- ables. linksm = 0 on device reset. ??? 04 30113 rxhr_bb receive half rate selection bit, bank b, channel b. when rxhr = 1, the rbc[1:0] clocks are issued at half the scheduled rate of the reference clock. rxhr = 0 on device reset. pwrdnr_bb receiver power down control bit, bank b, channel b. when pwrdnr = 1, sections of the receive hardware are powered down to conserve power. pwrdnr = 0 on device reset. sdovride_bb receive signal detect alarm over- ride bit, bank b, channel b. when sdovride = 1, the energy detector out- put from the receiver is masked. thus, when there is no receive data, the powerdown function is disabled and the corresponding sdon alarm is suppressed. sdovride = 1 on device reset. 8b10br_bb receive 8b/10b decoder enable bit, bank b, channel b. when 8b10br = 1, the 8b/10b decoder on the receive path is enabled. otherwise, it is bypassed. 8b10br = on device reset. linksm_bb link state machine enalbe bit, bank b, channel b. when linksm = 1, the receiver link state machine is enabled. otherwise, the link state machine is dis- ables. linksm = 0 on device reset. ??? 04 30123 rxhr_bc receive half rate selection bit, bank b, channel c. when rxhr = 1, the rbc[1:0] clocks are issued at half the scheduled rate of the reference clock. rxhr = 0 on device reset. pwrdnr_bc receiver power down control bit, bank b, channel c. when pwrdnr = 1, sections of the receive hardware are powered down to conserve power. pwrdnr = 0 on device reset. sdovride_bc receive signal detect alarm over- ride bit, bank b, channel c. when sdovride = 1, the energy detector out- put from the receiver is masked. thus, when there is no receive data, the powerdown function is disabled and the corresponding sdon alarm is suppressed. sdovride = 1 on device reset. 8b10br_bc receive 8b/10b decoder enable bit, bank b, channel c. when 8b10br = 1, the 8b/10b decoder on the receive path is enabled. otherwise, it is bypassed. 8b10br = on device reset. linksm_bc link state machine enalbe bit, bank b, channel c. when linksm = 1, the receiver link state machine is enabled. otherwise, the link state machine is dis- ables. linksm = 0 on device reset. ??? 04 30133 rxhr_bd receive half rate selection bit, bank b, channel d. when rxhr = 1, the rbc[1:0] clocks are issued at half the scheduled rate of the reference clock. rxhr = 0 on device reset. pwrdnr_bd receiver power down control bit, bank b, channel d. when pwrdnr = 1, sections of the receive hardware are powered down to conserve power. pwrdnr = 0 on device reset. sdovride_bd receive signal detect alarm over- ride bit, bank b, channel d. when sdovride = 1, the energy detector out- put from the receiver is masked. thus, when there is no receive data, the powerdown function is disabled and the corresponding sdon alarm is suppressed. sdovride = 1 on device reset. 8b10br_bd receive 8b/10b decoder enable bit, bank b, channel d. when 8b10br = 1, the 8b/10b decoder on the receive path is enabled. otherwise, it is bypassed. 8b10br = on device reset. linksm_bd link state machine enalbe bit, bank b, channel d. when linksm = 1, the receiver link state machine is enabled. otherwise, the link state machine is dis- ables. linksm = 0 on device reset. ??? 04
agere systems inc. 49 preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel memory map (continued) table 12. memory map (continued) addr (hex) reg # db0 db1 db2 db3 db4 db5 db6 db7 default value serdes b common transmit and receive channel configuration registers 30104 prbs_ba transmit and receive prbs enable bit, bank b, chan- nel a. when prbs = 1, the prbs genera- tor on the trans- mitter and the prbs checker on the receiver are enabled. prbs = 0 on device reset. mask_ba transmit and receive alarm mask bit, bank b, channel a. when mask = 1, the trans- mit and receive alarms of a channel are prevented from generating an inter- rupt. this mask bit overrides the individ- ual alarm mask bits in the alarm mask reg- isters. mask = 1 on device reset. swrst_ba transmit and receive software reset bit, bank b, channel a. when swrst = 1, this bit provides the same function as the hard- ware reset, except all configuration register settings are preserved. this is not a self-clear- ing bit. once set, this bit must be cleared by writ- ing a 0 to it. swrst = 0 on device reset. ???? testen_ba transmit and receive test enable bit, bank b, channel a. when testen = 1, the trans- mit and receive sections are placed in test mode. testen = 0 on device reset. when the global test enable bit gtes- ten = 0, the individual channel test enable bits are used to selectively place a channel in test or normal mode. when gtesten = 1, all channels are set to test mode regardless of their testen setting. 02 30114 prbs_bb transmit and receive prbs enable bit, bank b, chan- nel b. when prbs = 1, the prbs genera- tor on the trans- mitter and the prbs checker on the receiver are enabled. prbs = 0 on device reset. mask_bb transmit and receive alarm mask bit, bank b, channel b. when mask = 1, the trans- mit and receive alarms of a channel are prevented from generating an inter- rupt. this mask bit overrides the individ- ual alarm mask bits in the alarm mask reg- isters. mask = 1 on device reset. swrst_bb transmit and receive software reset bit, bank b, channel b. when swrst = 1, this bit provides the same function as the hard- ware reset, except all configuration register settings are preserved. this is not a self-clear- ing bit. once set, this bit must be cleared by writ- ing a 0 to it. swrst = 0 on device reset. ???? testen_bb transmit and receive test enable bit, bank b, channel b. when testen = 1, the trans- mit and receive sections are placed in test mode. testen = 0 on device reset. when the global test enable bit gtes- ten = 0, the individual channel test enable bits are used to selectively place a channel in test or normal mode. when gtesten = 1, all channels are set to test mode regardless of their testen setting. 02 30124 prbs_bc transmit and receive prbs enable bit, bank b, chan- nel c. when prbs = 1, the prbs genera- tor on the trans- mitter and the prbs checker on the receiver are enabled. prbs = 0 on device reset. mask_bc transmit and receive alarm mask bit, bank b, channel c. when mask = 1, the trans- mit and receive alarms of a channel are prevented from generating an inter- rupt. this mask bit overrides the individ- ual alarm mask bits in the alarm mask reg- isters. mask = 1 on device reset. swrst_bc transmit and receive software reset bit, bank b, channel c. when swrst = 1, this bit provides the same function as the hard- ware reset, except all configuration register settings are preserved. this is not a self-clear- ing bit. once set, this bit must be cleared by writ- ing a 0 to it. swrst = 0 on device reset. ???? testen_bc transmit and receive test enable bit, bank b, channel c. when testen = 1, the trans- mit and receive sections are placed in test mode. testen = 0 on device reset. when the global test enable bit gtes- ten = 0, the individual channel test enable bits are used to selectively place a channel in test or normal mode. when gtesten = 1, all channels are set to test mode regardless of their testen setting. 02 30134 prbs_bd transmit and receive prbs enable bit, bank b, chan- nel d. when prbs = 1, the prbs genera- tor on the trans- mitter and the prbs checker on the receiver are enabled. prbs = 0 on device reset. mask_bd transmit and receive alarm mask bit, bank b, channel d. when mask = 1, the trans- mit and receive alarms of a channel are prevented from generating an inter- rupt. this mask bit overrides the individ- ual alarm mask bits in the alarm mask reg- isters. mask = 1 on device reset. swrst_bd transmit and receive software reset bit, bank b, channel d. when swrst = 1, this bit provides the same function as the hard- ware reset, except all configuration register settings are preserved. this is not a self-clear- ing bit. once set, this bit must be cleared by writ- ing a 0 to it. swrst = 0 on device reset. ???? testen_bd transmit and receive test enable bit, bank b, channel d. when testen = 1, the trans- mit and receive sections are placed in test mode. testen = 0 on device reset. when the global test enable bit gtes- ten = 0, the individual channel test enable bits are used to selectively place a channel in test or normal mode. when gtesten = 1, all channels are set to test mode regardless of their testen setting. 02
50 agere systems inc. preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel memory map (continued) table 12. memory map (continued) addr (hex) reg # db0 db1 db2 db3 db4 db5 db6 db7 default value serdes b global control register (acts on channels a, b, c, and d) 30105 gprbs_b global enable. the gprbs bit globally enables the prbs gener- ators and checkers all four channels of serdes b when gprbs = 1. gprbs = 0 on device reset. gmask_b global mask. the gmask globally masks all the channel alarms of serdes b when gmask = 1. this pre- vents all the transmit and receive alarms from generating an interrupt. gmask = 1 on device reset. gswrst_b reset func- tion. the gswrst bit provides the same function as the hardware reset for the transmit and receive sec- tions of all four channels of aserdes b, except that the device configu- ration settings are not affected when gswrst is asserted. gswrst = 0 on device reset. this is not a self-clearing bit. once set, it must be cleared by writing a 0 to it. gpwrdnt_b powerdown transmit func- tion. when gpwrdnt = 1, sections of the transmit hardware for all four chan- nels of ser- des b are powered down to conserve power. gpwrdnt = 0 on device reset. gpwrdnr_b powerdown receive func- tion. when gpwrdnr = 1, sections of the receive hardware for all four chan- nels of ser- des b are powered down to conserve power. gpwrdnr = 0 on device reset. gtristn_b active-low tristn func- tion. when gtristn = 0, the cmos out- put buffers for serdes b are 3-stated. gtristn = 1 on device reset. ? gtesten_b test enable control. when gtesten = 1, the transmit and receive sec- tions of all four channels of serdes b are placed in test mode. gtes- ten = 0 on device reset. 22
agere systems inc. 51 preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel memory map (continued) table 12. memory map (continued) addr (hex) reg # db0 db1 db2 db3 db4 db5 db6 db7 default value control registers b 30900 b0 enbysync_b a byte align- ments bank b, c h a n n e l a enbysync_b b byte align- ments bank b, channel b enbysync_b c byte align- ments bank b, channel c enbysync_b d byte align- ments bank b, channel d lckrefn_ba lock receiver to ref. clock for bank b channel a lckrefn_bb lock receiver to ref. clock for bank b channel b lckrefn_bc lock receiver to ref. clock for bank b channel c lckrefn_bd lock receiver to ref. clock for bank b channel d 00 30901 b1 loopenb_ba enable loop- back mode for bank b, chan- nel a loopenb_bb enable loop- back mode for bank b, chan- nel b loopenb_bc enable loop- back mode for bank b, chan- nel c loopenb_bd enable loop- back mode for bank b, chan- nel d nowdalign_ ba defeats demux alignment for bank b, chan- nel a nowdalign_ bb defeats demux alignment for bank b, chan- nel b nowdalign_ bc defeats demux alignment for bank b, chan- nel c nowdalign_ bd defeats demux alignment for bank b, chan- nel d 00 30902 b2 reserved for future use 30903 b3 reserved for future use 30910 b4 dowdalign_ ba force new demux word alignment for bank b, chan- nel a dowdalign_ bb force new demux word alignment for bank b, chan- nel b dowdalign _bc force new demux word alignment for bank b, chan- nel c dowdalign_ bd force new demux word alignment for bank b, chan- nel d fmpu_str_e n_ba enable align- ment function for channel ba fmpu_str_e_ bb enable align- ment function for channel bb fmpu_str_e n_bc enable align- ment function for channel bc fmpu_str_e n_bd enable align- ment function for channel bd 00 30911 b5 fmpu_synmode_ba sync mode for ba fmpu_synmode_bb sync mode for bb fmpu_synmode_bc sync mode for bc fmpu_synmode_bd sync mode for bd 00 30912 b6 reserved for future use 30913 b7 reserved for future use 30920 b8 fmpu_resyn c1_ba resync a single channel, ba. write a 0, then write a 1. fmpu_resyn c1_bb resync a single channel, bb. write a 0, then write a 1. fmpu_resyn c1_bc resync a single channel, bc. write a 0, then write a 1. fmpu_resyn c1_bd resync a single channel, bd. write a 0, then write a 1. fmpu_resyn c2_b1 resync 2 chan- nels, ba and bb. write a 0, then write a 1. fmpu_resyn c2_b2 resync 2 chan- nels, bc and bd. write a 0, then write a 1. fmpu_resyn c4_b resync 4 chan- nels b[a:d]. write a 0, then write a 1. xaui_mode b controls use of xaui link state machine vs. serdes link state machine for bank b 00 30921 b9 nochalgn b bypass chan- nel alignment demuxed data directly to fpga for bank b reserved for future use 00 30922 b10 reserved for future use 30923 b11 reserved for future use 30930 b12 reserved for future use 30931 b13 reserved for future use 30932 b14 reserved for future use 30933 b15 reserved for future use schar_chan select channel to test schar_txsel select tx option schar_ena enable charac- terization of serdes b 00
52 agere systems inc. preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel memory map (continued) table 12. memory map (continued) * for xauistat_by (address 0x30904), the definitions of these bits are: 00 ? no synchronization. 01 ? synchronization done. 10 ? synchronization done no comma has been detected. 11 ? not used. addr (hex) reg # db0 db1 db2 db3 db4 db5 db6 db7 default value status register b 30904 b16 xauistat_ba* status of xaui link state machine for bank b, channel a xauistat_bb* status of xaui link state machine for bank b, channel b xauistat_bc* status of xaui link state machine for bank b, channel c xauistat_bd* status of xaui link state machine for bank b, channel d 00 30905 b17 demuxwas_ ba status of demux word alignment for bank b, chan- nel a demuxwas_ bb status of demux word alignment for bank b, chan- nel b demuxwas_ bc status of demux word alignment for bank b, chan- nel c demuxwas_ bd status of demux word alignment for bank b, chan- nel d ch248_sync _ba alignment completed for ba ch248_sync _bb alignment completed for bb ch248_sync _bc alignment completed for bc ch248_sync _bd alignment completed for bd 00 30906 b18 reserved for future use 30907 b19 reserved for future use 30914 b20 sync2_b1_o vfl alignment fifo overflow for ba and bb sync2_b2_o vfl alignment fifo overflow for bd and bc sync4_b_ov fl alignment fifo overflow for b[a:d] sync2_b1_o os alignment out of sync for bb and ba sync2_b2_o os alignment out of sync for bc and bd sync4_b_o os alignment out of sync for b[a:d] reserved for future use 00 30915 b21 reserved for future use 30916 b22 reserved for future use 30917 b23 reserved for future use 30924 b24 reserved for future use 30925 b25 reserved for future use 30926 b26 reserved for future use 30927 b27 reserved for future use 30934 b28 reserved for future use 30935 b29 reserved for future use 30936 b30 reserved for future use 30937 b31 reserved for future use
agere systems inc. 53 preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel memory map (continued) table 12. memory map (continued) addr (hex) reg # db0 db1 db2 db3 db4 db5 db6 db7 default value common control registers 30a00 c0 tcksela controls source of 78 mhz tck78 for bank a rcksela controls source of 78 mhz rck78 for bank a tckselb controls source of 78 mhz tck78 for bank b rckselb controls source of 78 mhz rck78 for bank b 00 30a01 c1 reserved for future use rx_fifo_mi n threshold for low address in rx_fifo ? s 00 30a02 c2 rx_fifo_min threshold for low address in rx_fifo ? s fmpu_resy nc8 resync 8 channels, a[a:d], b[a:d] reserved for future use 00 common status registers 30a04 c4 sync8_ovfl alignment fifo overflow for a[a:d], b[a:d] sync8_oos alignment out of sync for a[a:d], b[a:d] reserved for future use 00 30a05 c5 reserved for future use
54 agere systems inc. preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel absolute maximum ratings stresses in excess of the absolute maximum ratings can cause permanent damage to the device. these are abso- lute stress ratings only. functional operation of the device is not implied at these or any other conditions in excess of those given in the operations sections of this data sheet. exposure to absolute maximum ratings for extended periods can adversely affect device reliability. the orca series 4 fpscs include circuitry designed to protect the chips from damaging substrate injection cur- rents and to prevent accumulations of static charge. nevertheless, conventional precautions should be observed during storage, handling, and use to avoid exposure to excessive electrical stress. table 13 . absolute maximum ratings recommended operating conditions table 14 . recommended operating conditions * for recommended operating conditions for v dd io, see the series 4 fpga data sheet and the series 4 i/o buffer application note. hsi electrical and timing characteristics table 15. absolute maximum ratings table 16. recommended operating conditions parameter symbol min max unit storage temperature t stg ? 65 150 c power supply voltage with respect to ground v dd 33 ? 0.3 4.2 v v dd io ? 0.3 4.2 v v dd 15 ? 2v input signal with respect to ground v in v ss ? 0.3 v ddio + 0.3 v signal applied to high-impedance output ? v ss ? 0.3 v ddio + 0.3 v maximum package body temperature ?? 220 c parameter symbol min max unit power supply voltage with respect to ground* v dd 33 2.7 3.6 v v dd 15 1.4 1.6 v input voltages v in v ss ? 0.3 v ddio + 0.3 v junction temperature t j ? 40 125 c parameter conditions min typ max unit power dissipation serdes and i/o (per channel) ?? 225 mw 8b/10b encoder/decoder (per channel) ?? 50 mw parameter conditions min typ max unit v dd 15 supply voltage ? 1.4 ? 1.6 v
agere systems inc. 55 preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel hsi electrical and timing characteristics (continued) 2391(f) figure 19. receive data eye-diagram template (differential) figure 19 provides a graphical characterization of the serdes receiver input requirements. it provides guidance on a number of input parameters, including signal amplitude and rise time lints, noise and jitter limits, and p and n input skew tolerance. it is believed that incoming data patterns falling within the shaded region of the template will be received without error (ber < 10e-12). data pattern eye-opening at the receive end of a link is considered the ultimate measures of received signal qual- ity. almost all detrimental characteristics of transmit signal and the interconnection link design result in eye-closure. this combined with the eye-opening limitations of the line receiver can provide a good indication of a links ability to transfer data error-free. signal jitter is of special interest to system designers. it is often the primary limiting characteristic of long digital links and of systems with high noise level environments. an interesting characteristic of the clock and data recov- ery (cdr) portion of the ort82g5 serdes receiver is its ability to filter incoming signal jitter that is below the clock recover bandwidth (estimated to be about 3 mhz). for signals with high levels of low frequency jitter the receiver can detect incoming data, error-free, with eye-openings significantly less than that of figure 19. this phe- nomena has been observed in the laboratory. eye-diagram measurement and simulation are excellent tools of design. they are both highly recommended when designing serial link interconnections and evaluating signal integrity. table 17. receiver specifications parameter conditions min typ max unit input data stream of nontransitions ??? 60 bits phase change, input signal ??? tbd ps eye opening ? 0.4 ?? u ip-p jitter tolerance ? tbd u ip-p 0.4ui 200 mv @ 1.0 ? 2.5 gbits/s, 1.2 v ui 350 mv @ 3.125 gbits/s
56 agere systems inc. preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel hsi electrical and timing characteristics (continued) table 18. reference clock specifications (refinp and refinn) table 19. channel output jitter (1.25 gbits/s) table 20. channel output jitter (2.5 gbits/s) table 21. serial output timing levels (cml i/o) table 22. serial input timing and levels (cml i/o) parameter min typ max unit frequency range 100 ? 156.25 mhz frequency tolerance ? 100 ? 100 ppm duty cycle (measured at 50% amplitude point) 40 50 60 % rise time ?? 500 ps fall time ?? 500 ps differential amplitude 500 ? 1000 mv p-p common mode level 0.5 ? 1.0 v single-ended amplitude 1.0 ? 1.5 v input capacitance (single ended) ? 20 ? pf in-band jitter (2.5 gbits/s) ?? 20 ps p-p in-band jitter (1.25 gbits/s) ?? 40 ps p-p out-of-band jitter ?? tbd ps p-p parameter min typ max unit deterministic ? tbd 0.08 ui p-p random ? tbd 0.12 ui p-p to t a l ? tbd 0.2 ui p-p parameter min typ max unit deterministic ? tbd 0.1 ui p-p random ? tbd 0.14 ui p-p to t a l ? tbd 0.24 ui p-p parameter min typ max unit rise time (20% ? 80%) 100 150 ? ps fall time (80% ? 20%) 100 150 ? ps common mode ? 1.25 ? v differential swing (full amplitude) 800 1000 1200 mv p-p differential swing (half amplitude) 400 500 600 mv p-p output load 50 ? 75 ? parameter min typ max unit rise time ? 150 ? ps fall time ? 150 ? ps differential swing 175 ? 1200 mv p-p common mode level 0.6 ? 0.9 v signal detect threshold ? tbd ? v
agere systems inc. 57 preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel pin information this section describes the pins and signals that perform fpga-related functions. during configuration, the user- programmable i/os are 3-stated and pulled up with an internal resistor. if any fpga function pin is not used (or not bonded to package pin), it is also 3-stated and pulled up after configuration. table 23 . fpga common-function pin description * the fpga states of operation section contains more information on how to control these signals during start-up. the timing of done release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the activation of all user i/os) is controlled by a second set of options. symbol i/o description dedicated pins v dd 33 ? 3 v positive power supply. v dd 15 ? 1.5 v positive power supply for internal logic. v ddio ? positive power supply used by i/o banks. gnd ? ground supply. ptemp i temperature sensing diode pin. dedicated input. reset i during configuration, reset forces the restart of configuration and a pull-up is enabled. after configuration, reset can be used as a general fpga input or as a direct input, which causes all plc latches/ffs to be asynchronously set/reset. cclk i o in the master and asynchronous peripheral modes, cclk is an output which strobes con- figuration data in. in the slave or readback after configuration, cclk is input synchronous with the data on din or d[7:0]. cclk is an output for daisy-chain operation when the lead device is in master, peripheral, or system bus modes. done i as an input, a low level on done delays fpga start-up after configuration.* o as an active-high, open-drain output, a high level on this signal indicates that configura- tion is complete. done has an optional pull-up resistor. prgm i prgm is an active-low input that forces the restart of configuration and resets the bound- ary scan circuitry. this pin always has an active pull-up. rd_cfg i this pin must be held high during device initialization until the init pin goes high. this pin always has an active pull-up. during configuration, rd_cfg is an active-low input that activates the ts_all function and 3-states all of the i/o. after configuration, rd_cfg can be selected (via a bit stream option) to activate the ts_all function as described above, or, if readback is enabled via a bit stream option, a high-to-low transition on rd_cfg will initiate readback of the configuration data, including pfu output states, starting with frame address 0. rd_data/tdo o rd_data/tdo is a dual-function pin. if used for readback, rd_data provides configura- tion data out. if used in boundary scan, tdo is test data out. cfg_irq /mpi_irq o during jtag, slave, master, and asynchronous peripheral configuration assertion on this cfg_irq (active-low) indicates an error or errors for block ram or fpsc initialization. mpi active-low interrupt request output.
58 agere systems inc. preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel pin information (continued) table 23. fpga common-function pin description (continued) * the fpga states of operation section contains more information on how to control these signals during start-up. the timing of done release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the activation of all user i/os) is controlled by a second set of options. symbol i/o description special-purpose pins (can also be used as a general i/o.) m[3:0] i during powerup and initialization, m0 ? m3 are used to select the configuration mode with their values latched on the rising edge of init . during configuration, a pull-up is enabled. i/o after configuration, these pins are user-programmable i/o.* pll_ck[0:7] i/o dedicated pcm clock pins. these pins are user-programmable i/o pins if not used by plls. p[tbtr]clk[1:0][ tc] i/o pins dedicated for the primary clock. input pins on the middle of each side with differential pairing. they may be used as general i/o pins if not needed for clocking purposes. tdi, tck, tms i if boundary scan is used, these pins are test data in, test clock, and test mode select inputs. if boundary scan is not selected, all boundary scan functions are inhibited once configura- tion is complete. even if boundary scan is not used, either tck or tms must be held at logic 1 during configuration. each pin has a pull-up enabled during configuration. i/o after configuration, these pins are user-programmable i/o.* rdy/busy /rclk o during configuration in peripheral mode, rdy/rclk indicates another byte can be written to the fpga. if a read operation is done when the device is selected, the same status is also available on d7 in asynchronous peripheral mode. after configuration, if the mpi is not used, this pin is a user-programmable i/o pin.* i/o during the master parallel configuration mode, rclk is a read output signal to an external memory. this output is not normally used. hdc o high during configuration is output high until configuration is complete. it is used as a con- trol output, indicating that configuration is not complete. i/o after configuration, this pin is a user-programmable i/o pin.* ldc o low during configuration is output low until configuration is complete. it is used as a control output, indicating that configuration is not complete. i/o after configuration, this pin is a user-programmable i/o pin.* init i/o init is a bidirectional signal before and during configuration. during configuration, a pull-up is enabled, but an external pull-up resistor is recommended. as an active-low, open-drain output, init is held low during power stabilization and internal clearing of memory. as an active-low input, init holds the fpga in the wait-state before the start of configuration. after configuration, this pin is a user-programmable i/o pin.* cs0 , cs1 i cs0 and cs1 are used in the asynchronous peripheral, slave parallel, and microprocessor configuration modes. the fpga is selected when cs0 is low and cs1 is high. during con- figuration, a pull-up is enabled. i/o after configuration, these pins are user-programmable i/o pins.* rd /mpi_strb ird is used in the asynchronous peripheral configuration mode. a low on rd changes d7 into a status output. as a status indication, a high indicates ready, and a low indicates busy. wr and rd should not be used simultaneously. if they are, the write strobe overrides. this pin is also used as the mpi data transfer strobe. i/o after configuration, if the mpi is not used, this pin is a user-programmable i/o pin.*
agere systems inc. 59 preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel pin information (continued) table 23. fpga common-function pin description (continued) * the fpga states of operation section contains more information on how to control these signals during start-up. the timing of done release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the activation of all user i/os) is controlled by a second set of options. symbol i/o description ppc_a[14:31] a[17:0] mpi_burst mpi_bdip mpi_tsz[1:0] a[21:0] i during mpi mode, the ppc_a[14:31] are used as the address bus driven by the powerpc bus master utilizing the least significant bits of the powerpc 32-bit address. o during master parallel configuration mode, a[14:31] address the configuration eprom. in mpi mode, many of the a[n] pins have alternate uses as described below. see the special function blocks section for more mpi information. during configuration, if not in master par- allel or an mpi configuration mode, these pins are 3-stated with a pull-up enabled. mpi_burst is driven low to indicate a burst transfer is in progress. driven high indicates that the current transfer is not a burst. mpi_bdip is driven by the powerpc processor assertion of this pin indicates that the sec- ond beat in front of the current one is requested by the master. negated before the burst transfer ends to abort the burst data phase. mpi_tsz[1:0] signals and are driven by the bus master to indicate the data transfer size for the transaction. set 01 for byte, 10 for half-word, and 00 for word. during master parallel mode a[14:31], mpi_burst, mpi_bdip, and mpi_tsz address the configuration eproms up to 4 mbytes. if not used for mpi, these pins are user-programmable i/o pins.* mpi_ack oin powerpc mode mpi operation, this is driven low indicating the mpi received the data on the write cycle or returned data on a read cycle. mpi_clk i this is the powerpc synchronous, positive-edge bus clock used for the mpi interface. it can be a source of the clock for the embedded system bus. if mpi is used, this can be the amba bus clock. mpi_tea o a low on the mpi transfer error acknowledge indicates that the mpi detects a bus error on the internal system bus for the current transaction. mpi_rtry o this pin requests the mpc860 to relinquish the bus and retry the cycle. d[0:31] i/o selectable data bus width from 8-, 16-, 32-bit. driven by the bus master in a write transac- tion. driven by mpi in a read transaction. i d[7:0] receive configuration data during master parallel, peripheral, and slave parallel con- figuration modes and each pin has a pull-up enabled. during serial configuration modes, d0 is the din input. d[7:3] output internal status for asynchronous peripheral mode when rd is low. after configuration, the pins are user-programmable i/o pins.* dp[0:3] i/o selectable parity bus width from 1, 2, 4-bit, dp[0] for d[0:7], dp[1] for d[8:15], dp[2] for d[16:23], and dp[3] for d[24:32]. after configuration, this pin is a user-programmable i/o pin.* din i during slave serial or master serial configuration modes, din accepts serial configuration data synchronous with cclk. during parallel configuration modes, din is the d0 input. during configuration, a pull-up is enabled. i/o after configuration, this pin is a user-programmable i/o pin.* dout o during configuration, dout is the serial data output that can drive the din of daisy-chained slave devices. data out on dout changes on the rising edge of cclk. i/o after configuration, dout is a user-programmable i/o pin.*
60 agere systems inc. preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel pin information (continued) this section describes device i/o signals to/from the embedded core excluding the signals at the cic boundary. table 24. fpsc function pin description symbol i/o description common signals for both serdes a and b pasb_resetn i reset. pasb_tristn i 3-state output buffers. pasb_pdn i power down. pasb_testclk i clock input for bist and loopback test. pbist_test_enn i selection of pasb_testclk input for bist test. ploop_test_enn i selection of pasb_testclk input for loopback test. pmp_testclk i clock input for microprocessor in test mode. pmp_testclk_enn i selection of pmp_testclk in test mode. psys_dobistn i input to start bist test. psys_rssig_all o output result of bist test. serdes a and b pins refclkn_a i cml reference clock input ? serdes a. refclkp_a i cml reference clock input ? serdes a. refclkn_b i cml reference clock input ? serdes b. refclkp_b i cml reference clock input ? serdes b. rext_a i reference resistor - serdes a. rext_b i reference resistor - serdes b. rextn_a i reference resistor - serdes a. a 3.32 k ? 1% resistor must be con- nected across rext_a and rextn_a. rextn_b i reference resistor ? serdes b. a 3.32 k ? 1% resistor must be con- nected across rext_b and rextn_b. hdinn_aa i high-speed cml receive data input ? serdes a, channel a. hdinp_aa i high-speed cml receive data input ? serdes a, channel a. hdinn_ab i high-speed cml receive data input ? serdes a, channel b. hdinp_ab i high-speed cml receive data input ? serdes a, channel b. hdinn_ac i high-speed cml receive data input ? serdes a, channel c. hdinp_ac i high-speed cml receive data input ? serdes a, channel c. hdinn_ad i high-speed cml receive data input ? serdes a, channel d. hdinp_ad i high-speed cml receive data input ? serdes a, channel d. hdinn_ba i high-speed cml receive data input ? serdes b, channel a. hdinp_ba i high-speed cml receive data input ? serdes b, channel a. hdinn_bb i high-speed cml receive data input ? serdes b, channel b. hdinp_bb i high-speed cml receive data input ? serdes b, channel b. hdinn_bc i high-speed cml receive data input ? serdes b, channel c. hdinp_bc i high-speed cml receive data input ? serdes b, channel c. hdinn_bd i high-speed cml receive data input ? serdes b, channel d. hdinp_bd i high-speed cml receive data input ? serdes b, channel d.
agere systems inc. 61 preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel pin information (continued) table 24. fpsc function pin description (continued) symbol i/o description serdes a and b pins hdoutn_aa o high-speed cml transmit data output ? serdes a, channel a. hdoutp_aa o high-speed cml transmit data output ? serdes a, channel a. hdoutn_ab o high-speed cml transmit data output ? serdes a, channel b. hdoutp_ab o high-speed cml transmit data output ? serdes a, channel b. hdoutn_ac o high-speed cml transmit data output ? serdes a, channel c. hdoutp_ac o high-speed cml transmit data output ? serdes a, channel c. hdoutn_ad o high-speed cml transmit data output ? serdes a, channel d. hdoutp_ad o high-speed cml transmit data output ? serdes a, channel d. hdoutn_ba o high-speed cml transmit data output ? serdes b, channel a. hdoutp_ba o high-speed cml transmit data output ? serdes b, channel a. hdoutn_bb o high-speed cml transmit data output ? serdes b, channel b. hdoutp_bb o high-speed cml transmit data output ? serdes b, channel b. hdoutn_bc o high-speed cml transmit data output ? serdes b, channel c. hdoutp_bc o high-speed cml transmit data output ? serdes b, channel c. hdoutn_bd o high-speed cml transmit data output ? serdes b, channel d. hdoutp_bd o high-speed cml transmit data output ? serdes b, channel d. power and ground v dd ib_aa ? 1.8 v/1.5 v power supply for high-speed serial input buffers. v dd ib_ab ? 1.8 v/1.5 v power supply for high-speed serial input buffers. v dd ib_ac ? 1.8 v/1.5 v power supply for high-speed serial input buffers. v dd ib_ad ? 1.8 v/1.5 v power supply for high-speed serial input buffers. v dd ib_ba ? 1.8 v/1.5 v power supply for high-speed serial input buffers. v dd ib_bb ? 1.8 v/1.5 v power supply for high-speed serial input buffers. v dd ib_bc ? 1.8 v/1.5 v power supply for high-speed serial input buffers. v dd ib_bd ? 1.8 v/1.5 v power supply for high-speed serial input buffers. v dd ob_aa ? 1.8 v/1.5 v power supply for high-speed serial output buffers. v dd ob_ab ? 1.8 v/1.5 v power supply for high-speed serial output buffers.
62 agere systems inc. preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel pin information (continued) table 24. fpsc function pin description (continued) symbol i/o description v dd ob_ac ? 1.8 v/1.5 v power supply for high-speed serial output buffers. v dd ob_ad ? 1.8 v/1.5 v power supply for high-speed serial output buffers. v dd ob_ba ? 1.8 v/1.5 v power supply for high-speed serial output buffers. v dd ob_bb ? 1.8 v/1.5 v power supply for high-speed serial output buffers. v dd ob_bc ? 1.8 v/1.5 v power supply for high-speed serial output buffers. v dd ob_bd ? 1.8 v/1.5 v power supply for high-speed serial output buffers. v ss rx_aa ? serdes analog receive circuitry ground. v ss rx_ab ? serdes analog receive circuitry ground. v ss rx_ac ? serdes analog receive circuitry ground. v ss rx_ad ? serdes analog receive circuitry ground. v ss rx_ba ? serdes analog receive circuitry ground. v ss rx_bb ? serdes analog receive circuitry ground. v ss rx_bc ? serdes analog receive circuitry ground. v ss rx_bd ? serdes analog receive circuitry ground. v ss gb_a ? guard band ground. v ss gb_b ? guard band ground. v dd gb_a ? 1.5 v guard band power supply. v dd gb_b ? 1.5 v guard band power supply. v ss aux_a ? serdes auxiliary circuit ground (no external pin). v ss aux_b ? serdes auxiliary circuit ground. v ss ib_aa ? high-speed input receive buffer ground (no external pin). v ss ib_ab ? high-speed input receive buffer ground. v ss ib_ac ? high-speed input receive buffer ground. v ss ib_ad ? high-speed input receive buffer ground. v ss ib_ba ? high-speed input receive buffer ground. v ss ib_bb ? high-speed input receive buffer ground. v ss ib_bc ? high-speed input receive buffer ground. v ss ib_bd ? high-speed input receive buffer ground. v ss ob_aa ? high-speed output transmit buffer ground (no external pin). v ss ob_ab ? high-speed output transmit buffer ground. v ss ob_ac ? high-speed output transmit buffer ground. v ss ob_ad ? high-speed output transmit buffer ground. v ss ob_ba ? high-speed output transmit buffer ground. v ss ob_bb ? high-speed output transmit buffer ground. v ss ob_bc ? high-speed output transmit buffer ground. v ss ob_bd ? high-speed output transmit buffer ground. v ss tx_aa ? serdes analog transmit circuitry ground (no external pin). v ss tx_ab ? serdes analog transmit circuitry ground. v ss tx_ac ? serdes analog transmit circuitry ground. v ss tx_ad ? serdes analog transmit circuitry ground. v ss tx_ba ? serdes analog transmit circuitry ground.
agere systems inc. 63 preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel pin information (continued) table 24. fpsc function pin description (continued) power supplies for ort82g5 power supply descriptions table 25 shows the ort82g5 embedded core power supply connection groupings. the tx-rx digital power sup- plies are used for transmit and receive digital logic including the microprocessor logic. the tx-rx analog power supplies are used for high-speed analog circuitry between the i/o buffers and the digital logic. the rx input buffer power supplies are used to power the input (receive) buffers. the tx output buffer supplies are used to power the output (transmit) buffers. the rx and tx buffer power supplies can be independently set to 1.5 v or 1.8 v, depend- ing on the end application. the auxiliary and guard band supplies are independent connection brought out to pins. table 25. power supply pin groupings symbol i/o description v ss tx_bb ? serdes analog transmit circuitry ground. v ss tx_bc ? serdes analog transmit circuitry ground. v ss tx_bd ? serdes analog transmit circuitry ground. v dd rx_aa ? 1.5 v power supply for serdes analog receive circuitry. v dd rx_ab ? 1.5 v power supply for serdes analog receive circuitry. v dd rx_ac ? 1.5 v power supply for serdes analog receive circuitry. v dd rx_ad ? 1.5 v power supply for serdes analog receive circuitry. v dd rx_ba ? 1.5 v power supply for serdes analog receive circuitry. v dd rx_bb ? 1.5 v power supply for serdes analog receive circuitry. v dd rx_bc ? 1.5 v power supply for serdes analog receive circuitry. v dd rx_bd ? 1.5 v power supply for serdes analog receive circuitry. v dd aux_a ? 1.5 v power supply for serdes auxiliary circuit. v dd aux_b ? 1.5 v power supply for serdes auxiliary circuit. tx-rx digital 1.5 v tx-rx analog 1.5 v tx output buffers 1.5/1.8 v rx input buffers 1.5 v/1.8 v auxiliary 1.5 v guard band 1.5 v v dd 15 v dd rx_aa v dd ob_aa v dd ib_aa v dd aux_a v dd gb_a ? v dd tx_aa v dd ob_ab v dd ib_ab v dd aux_b v dd gb_b ? v dd rx_ab v dd ob_ac v dd ib_ac ?? ? v dd tx_ab v dd ob_ad v dd ib_ad ?? ? v dd rx_ac v dd ob_ba v dd ib_ba ?? ? v dd tx_ac v dd ob_bb v dd ib_bb ?? ? v dd rx_ad v dd ob_bc v dd ib_bc ?? ? v dd tx_ad v dd ob_bd v dd ib_bd ?? ? v dd rx_ba ???? ? v dd tx_ba ???? ? v dd rx_bb ???? ? v dd tx_bb ???? ? v dd rx_bc ???? ? v dd tx_bc ???? ? v dd rx_bd ???? ? v dd tx_bd ????
64 agere systems inc. preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel pin information (continued) recommended power supply connections ideally, a board should have four separate power supplies as described below: tx-rx digital auxiliary supplies. the tx-rx digital and auxiliary power supply nodes should be supplied by a 1.5 v source. a single 1.5 v source can supply power to tx-rx digital and auxiliary nodes. tx-rx analog, guardband supplies. a dedicated 1.5 v power supply should be provided to the analog power pins. this will allow the end user to mini- mize noise. the guard band pins can also be sourced from the analog power supplies. tx output buffers. the power supplies to the tx output buffers should be isolated from the rest of the board power supplies. special care must be taken to minimize noise when providing board level power to these output buffers. the power supply can be 1.5 v or 1.8 v depending on the end application. rx input buffers. the power supplies to the rx input buffers should be isolated from the rest of the board power supplies. special care must be taken to minimize noise when providing board level power to these input buffers. the power supply can be 1.5 v or 1.8 v depending on the end application. recommended power supply filtering scheme the board connections of the various serdes v dd and v ss pins are critical to system performance. an example demonstration board schematic is available at: http://www.agere.com/netcom/platform/fpsc.html#ort82g5 power supply filtering is in the form of: a parallel bypass capacitor network consisting of 10 uf, 0.1 uf, and 1.0 uf caps close to the power source. a parallel bypass capacitor network consisting of 0.01 uf and 0.1 uf close to the pin on the ort82g5. example connections are shown in figure 20. the naming convention for the power supply sources shown in the figure are as follows: supply_1.5 v ? tx-rx digital, auxiliary power pins. supply_v dd rx ? rx analog power pins, guard band power pins. supply v dd tx ? tx analog power pins. supply v dd ib ? input rx buffer power pins. supply_v dd ob ? output rx buffer power pins.
agere systems inc. 65 preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel pin information (continued) 2390(f) figure 20. power supply filtering 0.1 f 10 f vdd15 supply_1.5 v source pin supply_vddrx vddtx supply_vddtx vddib supply_vddib vddob supply_vddob - 1 network for every 2 pins - 1 network for every 2 pins - 1 network for vddaux_[a,b] - 1 each for vddgb_[a,b] - 1 network for every 2 pins - 1 network for every 2 pins - 1 network for every 2 pins 1 f 0.01 f 0.1 f 0.1 f 10 f 1 f 0.01 f 0.1 f vddrx 0.1 f 10 f 1 f 0.01 f 0.1 f 0.1 f 10 f 1 f 0.01 f 0.1 f 0.1 f 10 f 1 f 0.01 f 0.1 f
66 agere systems inc. preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel pin information (continued) in table 26, an input refers to a signal flowing into the embedded core and an output refers to a signal flowing out of the embedded core. table 26. embedded core/fpga interface signal description pin name i/o description memory block interface signals ar_a[10:0] i read address ? memory block a. ar_b[10:0] i read address ? memory block b. aw_a[10:0] i write address ? memory block a. aw_b[10:0] i write address ? memory block b. bytewn_a[3:0] i write control pins for byte-at-a-time write-memory block a. bytewn_b[3:0] i write control pins for byte-at-a-time write-memory block b. ckr_a i read clock ? memory block a. ckr_b i read clock ? memory block b. ckw_a i write clock ? memory block a. ckw_b i write clock ? memory block a. csr_a i read chip select ? memory block a. csr_b i read chip select ? memory block a. cswa_a i write chip select a ? memory block a. cswa_b i write chip select a ? memory block b. cswb_a i write chip select b ? memory block a. cswb_b i write chip select b ? memory block b. d_a[35:0] i data in ? memory block a d_b[35:0] i data in ? memory block b. q_a[35:0] o data out ? memory block a. q_b[35:0] o data out ? memory block b.
agere systems inc. 67 preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel pin information (continued) table 26. embedded core/fpga interface signal description (continued) pin name i/o description transmit path signals twdaa[31:0] i transmit data ? serdes a, channel a. twdab[31:0] i transmit data ? serdes a, channel b. twdac[31:0] i transmit data ? serdes a, channel c. twdad[31:0] i transmit data ? serdes a, channel d. twdba[31:0] i transmit data ? serdes b, channel a. twdbb[31:0] i transmit data ? serdes b, channel b. twdbc[31:0] i transmit data ? serdes b, channel c. twdbd[31:0] i transmit data ? serdes b, channel d. tcommaaa[3:0] i transmit comma character ? serdes a, channel a. tcommaab[3:0] i transmit comma character ? serdes a, channel b. tcommaac[3:0] i transmit comma character ? serdes a, channel c. tcommaad[3:0] i transmit comma character ? serdes a, channel d. tcommaba[3:0] i transmit comma character ? serdes b, channel a. tcommabb[3:0] i transmit comma character ? serdes b, channel b. tcommabc[3:0] i transmit comma character ? serdes b, channel c. tcommabd[3:0] i transmit comma character ? serdes b, channel d. tck78a o transmit low-speed clock to fpga ? serdes a. tck78b o transmit low-speed clock to fpga ? serdes b. tsysclka i low-speed transmit fifo clock ? serdes a. tsysclkb i low-speed transmit fifo clock ? serdes b.
68 agere systems inc. preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel pin information (continued) table 26. embedded core/fpga interface signal description (continued) pin name i/o description receive path signals mrwdaa[39:0] o receive data ? serdes a, channel a. mrwdab[39:0] o receive data ? serdes a, channel b. mrwdac[39:0] o receive data ? serdes a, channel c. mrwdad[39:0] o receive data ? serdes a, channel d. mrwdba[39:0] o receive data ? serdes b, channel a. mrwdbb[39:0] o receive data ? serdes b, channel b. mrwdbc[39:0] o receive data ? serdes b, channel c. mrwdbd[39:0] o receive data ? serdes b, channel d. rwckaa o low-speed receive clock ? serdes a, channel a. rwckab o low-speed receive clock ? serdes a, channel b. rwckac o low-speed receive clock ? serdes a, channel c. rwckad o low-speed receive clock ? serdes a, channel d. rwckba o low-speed receive clock ? serdes b, channel a. rwckbb o low-speed receive clock ? serdes b, channel b. rwckbc o low-speed receive clock ? serdes b, channel c. rwckbd o low-speed receive clock ? serdes b, channel d. rck78a o receive low-speed clock to fpga ? serdes a. rck78a o receive low-speed clock to fpga ? serdes b. rsys_clka i low-speed receive fifo clock ? serdes a. rsys_clkb i low-speed receive fifo clock ? serdes b. sys_rst_n i synchronous reset of the channel alignment blocks.
agere systems inc. 69 preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel pin information (continued) package pinouts table 27 provides the package pin and pin function for the ort82g5 fpsc and packages. the bond pad name is identified in the pio nomenclature used in the orca foundry design editor. the bank column provides informa- tion as to which output voltage level bank the given pin is in. the group column provides information as to the group of pins the given pin is in. this is used to show which vref pin is used to provide the reference voltage for single-ended limited-swing i/os. if none of these buffer types (such as sstl, gtl, hstl) are used in a given group, then the vref pin is available as an i/o pin. when the number of fpga bond pads exceeds the number of package pins, bond pads are unused. when the number of package pins exceeds the number of bond pads, package pins are left unconnected (no connects). when a package pin is to be left as a no connect for a specific die, it is indicated as a note in the device column for the fpga. the tables provide no information on unused pads.
70 agere systems inc. preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel pin information (continued) table 27. ort82g5 680-pin pbgam pinout bm680 v dd io bank vref group i/o pin description additional function bm680 pair ab20 ?? vss vss ?? c3 ?? v dd 33 v dd 33 ?? e4 ?? o prd_data rd_data/tdo ? f5 ?? i preset_n reset_n ? g5 ?? i prd_cfg_n rd_cfg_n ? d3 ?? i pprgrm_n prgrm_n ? a2 0 (tl) ? v dd io0 v dd io0 ?? f4 0 (tl) 7 io pl2d pll_ck0c/hppll l21c_a0 g4 0 (tl) 7 io pl2c pll_ck0t/hppll l21t_a0 b3 0 (tl) ? v dd io0 v dd io0 ?? c2 0 (tl) 7 io pl3d ? l22c_d0 b1 0 (tl) 7 io pl3c vref_0_07 l22t_d0 a1 ?? vss v ss ?? j5 0 (tl) 7 io pl4d d5 l23c_a0 h5 0 (tl) 7 io pl4c d6 l23t_a0 b7 0 (tl) ? v dd io0 v dd io0 ?? e3 0 (tl) 8 io pl4b ? l24c_a0 f3 0 (tl) 8 io pl4a vref_0_08 l24t_a0 c1 0 (tl) 8 io pl5d hdc l25c_d0 d2 0 (tl) 8 io pl5c ldc_n l25t_d0 a34 ?? v ss v ss ?? g3 0 (tl) 8 io pl5b ? l26c_d0 h4 0 (tl) 8 io pl5a ? l26t_d0 e2 0 (tl) 9 io pl6d testcfg l27c_d0 d1 0 (tl) 9 io pl6c d7 l27t_d0 c5 0 (tl) ? v dd io0 v dd io0 ?? f2 0 (tl) 9 io pl7d vref_0_09 l28c_d0 e1 0 (tl) 9 io pl7c a17/ppc_a31 l28t_d0 aa13 ?? v ss v ss ?? j4 0 (tl) 9 io pl7b ? l29c_d0 k5 0 (tl) 9 io pl7a ? l29t_d0 h3 0 (tl) 9 io pl8d cs0_n l30c_d0 g2 0 (tl) 9 io pl8c cs1 l30t_d0 c9 0 (tl) ? v dd io0 v dd io0 ?? l5 0 (tl) 9 io pl8b ? l31c_d0 k4 0 (tl) 9 io pl8a ? l31t_d0 h2 0 (tl) 10 io pl9d ? l32c_d0 j3 0 (tl) 10 io pl9c ? l32t_d0 aa14 ?? v ss v ss ?? m5 0 (tl) 10 io pl9b ?? f1 0 (tl) 10 io pl10d init_n l33c_a0 g1 0 (tl) 10 io pl10c dout l33t_a0
agere systems inc. 71 preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel pin information (continued) table 27. ort82g5 680-pin pbgam pinout (continued) bm680 v dd io bank vref group i/o pin description additional function bm680 pair k3 0 (tl) 10 io pl11d vref_0_10 l34c_d0 j2 0 (tl) 10 io pl11c a16/ppc_a30 l34t_d0 aa15 ?? v ss v ss ?? l4 0 (tl) 10 io pl11b ?? n5 7 (cl) 1 io pl12d a15/ppc_a29 l1c_d0 m4 7 (cl) 1 io pl12c a14/ppc_a28 l1t_d0 aa3 7 (cl) ? v dd io7 v dd io7 ?? l3 7 (cl) 1 io pl12b ? l2c_d0 k2 7 (cl) 1 io pl12a ? l2t_d0 h1 7 (cl) 1 io pl13d vref_7_01 l3c_a0 j1 7 (cl) 1 io pl13c d4 l3t_a0 v18 ?? v ss v ss ?? n4 7 (cl) 2 io pl13b ? l4c_d0 p5 7 (cl) 2 io pl13a ? l4t_d0 m3 7 (cl) 2 io pl14d rdy/busy_n/rclk l5c_d0 l2 7 (cl) 2 io pl14c vref_7_02 l5t_d0 ac2 7 (cl) ? v dd io7 v dd io7 ?? k1 7 (cl) 2 io pl14b ? l6c_a0 l1 7 (cl) 2 io pl14a ? l6t_a0 p4 7 (cl) 2 io pl15d a13/ppc_a27 l7c_a0 p3 7 (cl) 2 io pl15c a12/ppc_a26 l7t_a0 v19 ?? v ss v ss ?? m2 7 (cl) 2 io pl15b ? l8c_a0 m1 7 (cl) 2 io pl15a ? l8t_a0 n2 7 (cl) 3 io pl16d ? l9c_a0 n1 7 (cl) 3 io pl16c ? l9t_a0 n3 7 (cl) ? v dd io7 v dd io7 ?? r4 7 (cl) 3 io pl16b ?? p2 7 (cl) 3 io pl17d a11/ppc_a25 l10c_d0 r3 7 (cl) 3 io pl17c vref_7_03 l10t_d0 w16 ?? v ss v ss ?? r5 7 (cl) 3 io pl17b ?? p1 7 (cl) 3 io pl18d ? l11c_a0 r1 7 (cl) 3 io pl18c ? l11t_a0 t5 7 (cl) 3 io pl18b ? l12c_a0 t4 7 (cl) 3 io pl18a ? l12t_a0 t3 7 (cl) 4 io pl19d rd_n/mpi_strb_n l13c_a0 t2 7 (cl) 4 io pl19c vref_7_04 l13t_a0 w17 ?? v ss v ss ?? u1 7 (cl) 4 io pl19b ? l14c_a0 t1 7 (cl) 4 io pl19a ? l14t_a0 u4 7 (cl) 4 io pl20d plck0c l15c_a0
72 agere systems inc. preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel pin information (continued) table 27. ort82g5 680-pin pbgam pinout (continued) bm680 v dd io bank vref group i/o pin description additional function bm680 pair u5 7 (cl) 4 io pl20c plck0t l15t_a0 r2 7 (cl) ? v dd io7 v dd io7 ?? u2 7 (cl) 4 io pl20b ? l16c_d0 v1 7 (cl) 4 io pl20a ? l16t_d0 w18 ?? v ss v ss ?? v2 7 (cl) 5 io pl21d a10/ppc_a24 l17c_a0 v3 7 (cl) 5 io pl21c a9/ppc_a23 l17t_a0 w19 ?? v ss v ss ?? v4 7 (cl) 5 io pl21b ? l18c_a0 v5 7 (cl) 5 io pl21a ? l18t_a0 w4 7 (cl) 5 io pl22d a8/ppc_a22 l19c_a0 w3 7 (cl) 5 io pl22c vref_7_05 l19t_a0 w1 7 (cl) 5 io pl22b ? l20c_a0 y1 7 (cl) 5 io pl22a ? l20t_a0 y2 7 (cl) 5 io pl23d ? l21c_d0 aa1 7 (cl) 5 io pl23c ? l21t_d0 y13 ?? v ss v ss ?? y4 7 (cl) 5 io pl23b ? l22c_a0 y3 7 (cl) 5 io pl23a ? l22t_a0 y5 7 (cl) 6 io pl24d plck1c l23c_a0 w5 7 (cl) 6 io pl24c plck1t l23t_a0 u3 7 (cl) ? v dd io7 v dd io7 ?? ab1 7 (cl) 6 io pl24b ? l24c_d0 aa2 7 (cl) 6 io pl24a ? l24t_d0 ab2 7 (cl) 6 io pl25d vref_7_06 l25c_d0 ac1 7 (cl) 6 io pl25c a7/ppc_a21 l25t_d0 y14 ?? v ss v ss ?? aa4 7 (cl) 6 io pl25b ?? ab4 7 (cl) 6 io pl26d a6/ppc_a20 l26c_a0 ab3 7 (cl) 6 io pl26c a5/ppc_a19 l26t_a0 w2 7 (cl) ? v dd io7 v dd io7 ?? ad1 7 (cl) 7 io pl26b ?? ae1 7 (cl) 7 io pl27d wr_n/mpi_rw l27c_d0 ad2 7 (cl) 7 io pl27c vref_7_07 l27t_d0 ac3 7 (cl) 7 io pl27b ? l28c_a0 ac4 7 (cl) 7 io pl27a ? l28t_a0 af1 7 (cl) 8 io pl28d a4/ppc_a18 l29c_d0 ae2 7 (cl) 8 io pl28c vref_7_08 l29t_d0 ab5 7 (cl) 8 io pl29d a3/ppc_a17 l30c_a0 aa5 7 (cl) 8 io pl29c a2/ppc_a16 l30t_a0 y15 ?? v ss v ss ?? ad3 7 (cl) 8 io pl29b ??
agere systems inc. 73 preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel pin information (continued) table 27. ort82g5 680-pin pbgam pinout (continued) bm680 v dd io bank vref group i/o pin description additional function bm680 pair ag1 7 (cl) 8 io pl30d a1/ppc_a15 l31c_d0 af2 7 (cl) 8 io pl30c a0/ppc_a14 l31t_d0 ad4 7 (cl) 8 io pl30b ? l32c_d0 ae3 7 (cl) 8 io pl30a ? l32t_d0 ad5 7 (cl) 8 io pl31d dp0 l33c_a0 ac5 7 (cl) 8 io pl31c dp1 l33t_a0 y20 ?? v ss v ss ?? ag2 7 (cl) 8 io pl31b ? l34c_d0 ah1 7 (cl) 8 io pl31a ? l34t_d0 af3 6 (bl) 1 io pl32d d8 l1c_a0 ag3 6 (bl) 1 io pl32c vref_6_01 l1t_a0 al7 6 (bl) ? v dd io6 v dd io6 ?? ae4 6 (bl) 1 io pl32b ? l2c_a0 af4 6 (bl) 1 io pl32a ? l2t_a0 ae5 6 (bl) 1 io pl33d d9 l3c_a0 af5 6 (bl) 1 io pl33c d10 l3t_a0 r21 ?? v ss v ss ?? aj1 6 (bl) 2 io pl34d ? l4c_d0 ah2 6 (bl) 2 io pl34c vref_6_02 l4t_d0 am5 6 (bl) ? v dd io6 v dd io6 ?? ak1 6 (bl) 2 io pl34b ? l5c_d0 aj2 6 (bl) 2 io pl34a ? l5t_d0 r22 ?? v ss v ss ?? ag4 6 (bl) 3 io pl35b d11 l6c_d0 ah3 6 (bl) 3 io pl35a d12 l6t_d0 al1 6 (bl) 3 io pl36d ? l7c_d0 ak2 6 (bl) 3 io pl36c ? l7t_d0 am9 6 (bl) ? v dd io6 v dd io6 ?? am1 6 (bl) 3 io pl36b vref_6_03 l8c_d0 al2 6 (bl) 3 io pl36a d13 l8t_d0 aj3 6 (bl) 4 io pl37d ?? t16 ?? v ss v ss ?? aj4 6 (bl) 4 io pl37b ? l9c_a0 ah4 6 (bl) 4 io pl37a vref_6_04 l9t_a0 ak3 6 (bl) 4 io pl38c ?? an2 6 (bl) ? v dd io6 v dd io6 ?? ag5 6 (bl) 4 io pl38b ? l10c_a0 ah5 6 (bl) 4 io pl38a ? l10t_a0 an1 6 (bl) 4 io pl39d pll_ck7c/hppll l11c_d0 am2 6 (bl) 4 io pl39c pll_ck7t/hppll l11t_d0 t17 ?? v ss v ss ?? al3 6 (bl) 4 io pl39b ? l12c_d0
74 agere systems inc. preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel pin information (continued) table 27. ort82g5 680-pin pbgam pinout (continued) bm680 v dd io bank vref group i/o pin description additional function bm680 pair ak4 6 (bl) 4 io pl39a ? l12t_d0 t18 ?? v ss v ss ?? am3 ?? iptemp ptemp ? an3 6 (bl) ? v dd io6 v dd io6 ?? aj5 ?? i o lv d s _ r lv d s _ r ? al4 ?? v dd 33 v dd 33 ?? t19 ?? v ss v ss ?? ak5 ?? v dd 33 v dd 33 ?? am4 6 (bl) 5 io pb2a dp2 l13t_d0 al5 6 (bl) 5 io pb2b ? l13c_d0 an7 6 (bl) ? v dd io6 v dd io6 ?? ap3 6 (bl) 5 io pb2c pll_ck6t/ppll l14t_a0 ap4 6 (bl) 5 io pb2d pll_ck6c/ppll l14c_a0 an4 6 (bl) 5 io pb3b ?? u16 ?? v ss v ss ?? ak6 6 (bl) 5 io pb3c ? l15t_a0 ak7 6 (bl) 5 io pb3d ? l15c_a0 al6 6 (bl) 5 io pb4a vref_6_05 l16t_a0 am6 6 (bl) 5 io pb4b dp3 l16c_a0 ap1 6 (bl) ? v dd io6 v dd io6 ?? an5 6 (bl) 6 io pb4c ? l17t_a0 ap5 6 (bl) 6 io pb4d ? l17c_a0 ak8 6 (bl) 6 io pb5b ?? u17 ?? v ss v ss ?? ap6 6 (bl) 6 io pb5c vref_6_06 l18t_d0 ap7 6 (bl) 6 io pb5d d14 l18c_d0 am7 6 (bl) 6 io pb6a ? l19t_d0 an6 6 (bl) 6 io pb6b ? l19c_d0 ap2 6 (bl) ? v dd io6 v dd io6 ?? al8 6 (bl) 7 io pb6c d15 l20t_a0 al9 6 (bl) 7 io pb6d d16 l20c_a0 ak9 6 (bl) 7 io pb7b ?? u18 ?? v ss v ss ?? an8 6 (bl) 7 io pb7c d17 l21t_a0 am8 6 (bl) 7 io pb7d d18 l21c_a0 an9 6 (bl) 7 io pb8a ? l22t_d0 ap8 6 (bl) 7 io pb8b ? l22c_d0 ak10 6 (bl) 7 io pb8c vref_6_07 l23t_a0 al10 6 (bl) 7 io pb8d d19 l23c_a0 ap9 6 (bl) 8 io pb9b ?? u19 ?? v ss v ss ?? am10 6 (bl) 8 io pb9c d20 l24t_a0
agere systems inc. 75 preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel pin information (continued) table 27. ort82g5 680-pin pbgam pinout (continued) bm680 v dd io bank vref group i/o pin description additional function bm680 pair am11 6 (bl) 8 io pb9d d21 l24c_a0 ak11 6 (bl) 8 io pb10b ?? an10 6 (bl) 8 io pb10c vref_6_08 l25t_a0 ap10 6 (bl) 8 io pb10d d22 l25c_a0 an11 6 (bl) 9 io pb11a ? l26t_a0 ap11 6 (bl) 9 io pb11b ? l26c_a0 v16 ?? v ss v ss ?? al12 6 (bl) 9 io pb11c d23 l27t_a0 ak12 6 (bl) 9 io pb11d d24 l27c_a0 an12 6 (bl) 9 io pb12a ? l28t_a0 am12 6 (bl) 9 io pb12b ? l28c_a0 ap12 6 (bl) 9 io pb12c vref_6_09 l29t_a0 ap13 6 (bl) 9 io pb12d d25 l29c_a0 am13 6 (bl) 9 io pb13a ? l30t_d0 an14 6 (bl) 9 io pb13b ? l30c_d0 v17 ?? v ss v ss ?? ap14 6 (bl) 10 io pb13c d26 l31t_a0 ap15 6 (bl) 10 io pb13d d27 l31c_a0 ak13 6 (bl) 10 io pb14a ? l32t_a0 ak14 6 (bl) 10 io pb14b ? l32c_a0 am14 6 (bl) 10 io pb14c vref_6_10 l33t_a0 al14 6 (bl) 10 io pb14d d28 l33c_a0 ap17 6 (bl) 11 io pb15a ? l34t_a0 ap16 6 (bl) 11 io pb15b ? l34c_a0 am15 6 (bl) 11 io pb15c d29 l35t_d0 an16 6 (bl) 11 io pb15d d30 l35c_d0 am17 6 (bl) 11 io pb16a ? l36t_a0 am16 6 (bl) 11 io pb16b ? l36c_a0 ap18 6 (bl) 11 io pb16c vref_6_11 l37t_a0 ap19 6 (bl) 11 io pb16d d31 l37c_a0 al16 5 (bc) 1 io pb17a ? l1t_d0 ak15 5 (bc) 1 io pb17b ? l1c_d0 n22 ?? v ss v ss ?? an18 5 (bc) 1 io pb17c ? l2t_a0 an19 5 (bc) 1 io pb17d ? l2c_a0 ap20 5 (bc) 1 io pb18a ? l3t_a0 ap21 5 (bc) 1 io pb18b ? l3c_a0 al17 5 (bc) 1 io pb18c vref_5_01 l4t_d0 ak16 5 (bc) 1 io pb18d ? l4c_d0 p13 ?? v ss v ss ?? am19 5 (bc) 2 io pb19a ? l5t_a0 am18 5 (bc) 2 io pb19b ? l5c_a0
76 agere systems inc. preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel pin information (continued) table 27. ort82g5 680-pin pbgam pinout (continued) bm680 v dd io bank vref group i/o pin description additional function bm680 pair p14 ?? v ss v ss ?? an20 5 (bc) 2 io pb19c pbck0t l6t_a0 am20 5 (bc) 2 io pb19d pbck0c l6c_a0 ak17 5 (bc) 2 io pb20a ? l7t_d0 al18 5 (bc) 2 io pb20b ? l7c_d0 al11 5 (bc) ? v dd io5 v dd io5 ?? ap22 5 (bc) 2 io pb20c vref_5_02 l8t_d0 an21 5 (bc) 2 io pb20d ? l8c_d0 am22 5 (bc) 2 io pb21a ? l9t_a0 am21 5 (bc) 2 io pb21b ? l9c_a0 ap23 5 (bc) 3 io pb21c ? l10t_d0 an22 5 (bc) 3 io pb21d vref_5_03 l10c_d0 al19 5 (bc) 3 io pb22a ? l11t_d0 ak18 5 (bc) 3 io pb22b ? l11c_d0 p15 ?? v ss v ss ?? ap24 5 (bc) 3 io pb22c ? l12t_d0 an23 5 (bc) 3 io pb22d ? l12c_d0 ap25 5 (bc) 3 io pb23a ? l13t_a0 ap26 5 (bc) 3 io pb23b ? l13c_a0 al13 5 (bc) ? v dd io5 v dd io5 ?? al20 5 (bc) 3 io pb23c pbck1t l14t_d0 ak19 5 (bc) 3 io pb23d pbck1c l14c_d0 ak20 5 (bc) 3 io pb24a ? l15t_d0 al21 5 (bc) 3 io pb24b ? l15c_d0 p20 ?? v ss v ss ?? an24 5 (bc) 4 io pb24c ? l16t_d0 am23 5 (bc) 4 io pb24d ? l16c_d0 an26 5 (bc) 4 io pb25a ? l17t_a0 an25 5 (bc) 4 io pb25b ? l17c_a0 al15 5 (bc) ? v dd io5 v dd io5 ?? ak21 5 (bc) 4 io pb25c ? l18t_d0 al22 5 (bc) 4 io pb25d vref_5_04 l18c_d0 am24 5 (bc) 4 io pb26a ? l19t_d0 al23 5 (bc) 4 io pb26b ? l19c_d0 p21 ?? v ss v ss ?? ap27 5 (bc) 5 io pb26c ? l20t_a0 an27 5 (bc) 5 io pb26d vref_5_05 l20c_a0 al24 5 (bc) 5 io pb27a ? l21t_d0 am25 5 (bc) 5 io pb27b ? l21c_d0 an13 5 (bc) ? v dd io5 v dd io5 ?? ap28 5 (bc) 5 io pb27c ? l22t_a0 ap29 5 (bc) 5 io pb27d ? l22c_a0
agere systems inc. 77 preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel pin information (continued) table 27. ort82g5 680-pin pbgam pinout (continued) bm680 v dd io bank vref group i/o pin description additional function bm680 pair an29 5 (bc) 6 io pb28b ?? p22 ?? v ss v ss ?? am27 5 (bc) 6 io pb28c ? l23t_d0 an28 5 (bc) 6 io pb28d vref_5_06 l23c_d0 am26 5 (bc) 6 io pb29b ?? ak22 5 (bc) 6 io pb29c ? l24t_a0 ak23 5 (bc) 6 io pb29d ? l24c_a0 al25 5 (bc) 7 io pb30b ?? r13 ?? v ss v ss ?? ap30 5 (bc) 7 io pb30c ? l25t_a0 ap31 5 (bc) 7 io pb30d ? l25c_a0 ak24 5 (bc) 7 io pb31b ?? an15 5 (bc) ? v dd io5 v dd io5 ?? am29 5 (bc) 7 io pb31c vref_5_07 l26t_a0 am28 5 (bc) 7 io pb31d ? l26c_a0 an30 5 (bc) 7 io pb32b ?? r14 ?? v ss v ss ?? ak25 5 (bc) 7 io pb32c ? l27t_d0 al26 5 (bc) 7 io pb32d ? l27c_d0 an17 5 (bc) ? v dd io5 v dd io5 ?? al27 5 (bc) 8 io pb33c ? l28t_a0 al28 5 (bc) 8 io pb33d vref_5_08 l28c_a0 an31 5 (bc) 8 io pb34b ?? r15 ?? v ss v ss ?? ak26 5 (bc) 8 io pb34d ?? am30 5 (bc) 9 io pb35b ?? al29 5 (bc) 9 io pb35d vref_5_09 ? ak27 5 (bc) 9 io pb36b ?? r20 ?? v ss v ss ?? al30 5 (bc) 9 io pb36c ? l29t_d0 ak29 5 (bc) 9 io pb36d ? l29c_d0 ak28 ?? v dd 33 v dd 33 ?? aa16 ?? v dd 15 v dd 15 ?? ap32 ?? io pschar_ldio9 ?? ap33 ?? io pschar_ldio8 ?? an32 ?? io pschar_ldio7 ?? am31 ?? io pschar_ldio6 ?? aa17 ?? v dd 15 v dd 15 ?? am32 ?? v dd 33 v dd 33 ?? al31 ?? io pschar_ldio5 ?? am33 ?? io pschar_ldio4 ?? aa18 ?? v dd 15 v dd 15 ??
78 agere systems inc. preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel pin information (continued) table 27. ort82g5 680-pin pbgam pinout (continued) bm680 v dd io bank vref group i/o pin description additional function bm680 pair ak30 ?? io pschar_ldio3 ?? al32 ?? io pschar_ldio2 ?? aa19 ?? v dd 15 v dd 15 ?? ab16 ?? v dd 15 v dd 15 ?? ak31 ?? v dd 33 v dd 33 ?? aj30 ?? io pschar_ldio1 ?? ak33 ?? io pschar_ldio0 ?? ak34 ?? io pschar_ckio1 ?? aj31 ?? io pschar_ckio0 ?? aj33 ?? io pschar_xck ?? aj34 ?? io pschar_wdsync ?? ah30 ?? io pschar_cv ?? ah31 ?? io pschar_bytsync ?? ah32 ?? i atmout_b ?? ah33 ?? v ss gb_b v ss gb_b ?? ah34 ?? v dd gb_b v dd gb_b ?? aa32 ?? v dd rv dd aux_b ?? af30 ?? orext_b ?? af31 ?? orextn_b ?? ae30 ?? irefclkn_b ?? ae31 ?? i refclkp_b ?? ab32 ?? v ss tv ss aux_b ?? ad30 ?? v dd ib v dd ib_ba ?? ad32 ?? v dd rv dd rx_ba ?? af33 ?? i hdinn_ba ?? ac32 ?? v ss tv ss ib_ba ?? af34 ?? i hdinp_ba ?? ae32 ?? v dd rv dd rx_ba ?? ad31 ?? v ss rx v ss rx_ba ?? k32 ?? v dd rv dd tx_ba ?? ac30 ?? v dd ob v dd ob_ba ?? ae33 ?? o hdoutn_ba ?? af32 ?? v ss tv ss ob_ba ?? ae34 ?? o hdoutp_ba ?? ac30 ?? v dd ob v dd ob_ba ?? ag30 ?? v ss tv ss tx_ba ?? ab30 ?? v dd ib v dd ib_bb ?? ad33 ?? i hdinn_bb ?? ag31 ?? v ss tv ss ib_bb ?? ad34 ?? i hdinp_bb ?? ac31 ?? v ss rx v ss rx_bb ?? ab31 ?? v dd ob v dd ob_bb ??
agere systems inc. 79 preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel pin information (continued) table 27. ort82g5 680-pin pbgam pinout (continued) bm680 v dd io bank vref group i/o pin description additional function bm680 pair ac33 ?? o hdoutn_bb ?? ag32 ?? v ss tv ss ob_bb ?? ac34 ?? o hdoutp_bb ?? ab31 ?? v dd ob v dd ob_bb ?? ag33 ?? v ss tv ss tx_bb ?? aa30 ?? v dd ib v dd ib_bc ?? ab33 ?? i hdinn_bc ?? ag34 ?? v ss tv ss ib_bc ?? ab34 ?? i hdinp_bc ?? aa31 ?? v ss rx v ss rx_bc ?? y30 ?? v dd ob v dd ob_bc ?? aa33 ?? o hdoutn_bc ?? h30 ?? v ss tv ss ob_bc ?? aa34 ?? o hdoutp_bc ?? y31 ?? v dd ob v dd ob_bc ?? h31 ?? v ss tv ss tx_bc ?? w30 ?? v dd ib v dd ib_bd ?? y33 ?? i hdinn_bd ?? h32 ?? v ss tv ss ib_bd ?? y34 ?? i hdinp_bd ?? w31 ?? v ss rx v ss rx_bd ?? v30 ?? v dd ob v dd ob_bd ?? w33 ?? o hdoutn_bd ?? h33 ?? v ss tv ss ob_bd ?? w34 ?? o hdoutp_bd ?? v31 ?? v dd ob v dd ob_bd ?? h34 ?? v ss tv ss tx_bd ?? j32 ?? v ss tv ss tx_ad ?? u31 ?? v dd ob v dd ob_ad ?? t34 ?? o hdoutp_ad ?? m32 ?? v ss tv ss ob_ad ?? t33 ?? o hdoutn_ad ?? u30 ?? v dd ob v dd ob_ad ?? t31 ?? v ss rx v ss rx_ad ?? r34 ?? i hdinp_ad ?? n32 ?? v ss tv ss ib_ad ?? r33 ?? i hdinn_ad ?? t30 ?? v dd ib v dd ib_ad ?? u32 ?? v ss tv ss tx_ac ?? r31 ?? v dd ob v dd ob_ac ?? p34 ?? o hdoutp_ac ?? u33 ?? v ss tv ss ob_ac ??
80 agere systems inc. preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel pin information (continued) table 27. ort82g5 680-pin pbgam pinout (continued) bm680 v dd io bank vref group i/o pin description additional function bm680 pair p33 ?? o hdoutn_ac ?? r30 ?? v dd ob v dd ob_ac ?? p31 ?? v ss rx v ss rx_ac ?? n34 ?? i hdinp_ac ?? u34 ?? v ss tv ss ib_ac ?? n33 ?? i hdinn_ac ?? p30 ?? v dd ib v dd ib_ac ?? v32 ?? v ss tv ss tx_ab ?? n31 ?? v dd ob v dd ob_ab ?? m34 ?? o hdoutp_ab ?? v33 ?? v ss tv ss ob_ab ?? m33 ?? o hdoutn_ab ?? n31 ?? v dd ob v dd ob_ab ?? m31 ?? v ss rx v ss rx_ab ?? l34 ?? i hdinp_ab ?? v34 ?? v ss tv ss ib_ab ?? l33 ?? i hdinn_ab ?? n30 ?? v dd ib v dd ib_ab ?? m30 ?? v dd ob v dd ob_aa ?? k34 ?? o hdoutp_aa ?? k33 ?? o hdoutn_aa ?? m30 ?? v dd ob v dd ob_aa ?? l32 ?? v dd rv dd tx_aa ?? l31 ?? v ss rx v ss rx_aa ?? p32 ?? v dd rv dd rx_aa ?? j34 ?? i hdinp_aa ?? j33 ?? i hdinn_aa ?? r32 ?? v dd rv dd rx_aa ?? l30 ?? v dd ib v dd ib_aa ?? k31 ?? i refclkp_a ?? k30 ?? irefclkn_a ?? j31 ?? orextn_a ?? j30 ?? orext_a ?? y32 ?? v dd rv dd aux_a ?? g34 ?? v dd gb_a v dd gb_a ?? g33 ?? v ss gb_a v ss gb_a ?? g32 ?? i atmout_a ?? g31 ?? i preserve01 ?? f33 ?? i preserve02 ?? g30 ?? i preserve03 ?? f31 ?? o psys_rssig_all ?? f30 ?? i psys_dobistn ??
agere systems inc. 81 preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel pin information (continued) table 27. ort82g5 680-pin pbgam pinout (continued) bm680 v dd io bank vref group i/o pin description additional function bm680 pair e31 ?? v dd 33 v dd 33 ?? ab17 ?? v dd 15 v dd 15 ?? ab18 ?? v dd 15 v dd 15 ?? d32 ?? i pbist_test_enn ?? e30 ?? i ploop_test_enn ?? ab19 ?? v dd 15 v dd 15 ?? d31 ?? i pasb_pdn ?? c32 ?? i pmp_testclk ?? c31 ?? v dd 33 v dd 33 ?? aj32 ?? v dd 15 v dd 15 ?? b32 ?? i pasb_resetn ?? a33 ?? i pasb_tristn ?? b31 ?? i pmp_testclk_enn ?? a32 ?? i pasb_testclk ?? ak32 ?? v dd 15 v dd 15 ?? ab21 ?? v ss v ss ?? a31 ?? v dd 33 v dd 33 ?? b30 1 (tc) 7 io pt36d ?? ab22 ?? v ss v ss ?? c30 1 (tc) 7 io pt36b ?? d30 1 (tc) 7 io pt35d ?? b13 1 (tc) ? v dd io1 v dd io1 ?? e29 1 (tc) 7 io pt35b ?? e28 1 (tc) 7 io pt34d vref_1_07 ? an33 ?? v ss vss ?? d29 1 (tc) 8 io pt34b ?? b29 1 (tc) 8 io pt33d ? l1c_a0 c29 1 (tc) 8 io pt33c vref_1_08 l1t_a0 b15 1 (tc) ? v dd io1 v dd io1 ?? e27 1 (tc) 8 io pt32d ? l2c_a0 e26 1 (tc) 8 io pt32c ? l2t_a0 ap34 ?? vss vss ?? a30 1 (tc) 8 io pt32b ?? a29 1 (tc) 9 io pt31d ? l3c_d3 e25 1 (tc) 9 io pt31c vref_1_09 l3t_d3 b17 1 (tc) ? v dd io1 v dd io1 ?? e24 1 (tc) 9 io pt31a ?? b28 1 (tc) 9 io pt30d ? l4c_a0 c28 1 (tc) 9 io pt30c ? l4t_a0 b2 ?? vss vss ?? d28 1 (tc) 9 io pt30a ?? c27 1 (tc) 9 io pt29d ? l5c_a0
82 agere systems inc. preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel pin information (continued) table 27. ort82g5 680-pin pbgam pinout (continued) bm680 v dd io bank vref group i/o pin description additional function bm680 pair d27 1 (tc) 9 io pt29c ? l5t_a0 e23 1 (tc) 9 io pt29b ? l6c_a0 e22 1 (tc) 9 io pt29a ? l6t_a0 d26 1 (tc) 1 io pt28d ? l7c_a0 d25 1 (tc) 1 io pt28c ? l7t_a0 b33 ?? vss vss ?? d24 1 (tc) 1 io pt28b ? l8c_a0 d23 1 (tc) 1 io pt28a ? l8t_a0 c26 1 (tc) 1 io pt27d vref_1_01 l9c_a0 c25 1 (tc) 1 io pt27c ? l9t_a0 d11 1 (tc) ? v dd io1 v dd io1 ?? e21 1 (tc) 1 io pt27b ? l10c_a0 e20 1 (tc) 1 io pt27a ? l10t_a0 d22 1 (tc) 2 io pt26d ? l11c_a0 d21 1 (tc) 2 io pt26c vref_1_02 l11t_a0 e34 ?? vss vss ?? a28 1 (tc) 2 io pt26b ?? b26 1 (tc) 2 io pt25d ? l12c_a0 b25 1 (tc) 2 io pt25c ? l12t_a0 d13 1 (tc) ? v dd io1 v dd io1 ?? b27 1 (tc) 2 io pt25b ?? a27 1 (tc) 3 io pt24d ? l13c_a0 a26 1 (tc) 3 io pt24c vref_1_03 l13t_a0 n13 ?? vss vss ?? c24 1 (tc) 3 io pt24b ?? c22 1 (tc) 3 io pt23d ? l14c_a0 c23 1 (tc) 3 io pt23c ? l14t_a0 d15 1 (tc) ? v dd io1 v dd io1 ?? b24 1 (tc) 3 io pt23b ?? d20 1 (tc) 3 io pt22d ? l15c_a0 d19 1 (tc) 3 io pt22c ? l15t_a0 n14 ?? vss vss ?? e19 1 (tc) 3 io pt22b ? l16c_a0 e18 1 (tc) 3 io pt22a ? l16t_a0 c21 1 (tc) 4 io pt21d ? l17c_a0 c20 1 (tc) 4 io pt21c ? l17t_a0 a25 1 (tc) 4 io pt21b ? l18c_a0 a24 1 (tc) 4 io pt21a ? l18t_a0 b23 1 (tc) 4 io pt20d ? l19c_a0 a23 1 (tc) 4 io pt20c ? l19t_a0 n15 ?? vss vss ?? e17 1 (tc) 4 io pt20b ? l20c_a0
agere systems inc. 83 preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel pin information (continued) table 27. ort82g5 680-pin pbgam pinout (continued) bm680 v dd io bank vref group i/o pin description additional function bm680 pair e16 1 (tc) 4 io pt20a ? l20t_a0 b22 1 (tc) 4 io pt19d ? l21c_a0 b21 1 (tc) 4 io pt19c vref_1_04 l21t_a0 c18 1 (tc) 4 io pt19b ? l22c_a0 c19 1 (tc) 4 io pt19a ? l22t_a0 n20 ?? vss vss ?? a22 1 (tc) 5 io pt18d ptck1c l23c_a0 a21 1 (tc) 5 io pt18c ptck1t l23t_a0 n21 ?? vss vss ?? d17 1 (tc) 5 io pt18b ? l24c_a0 d18 1 (tc) 5 io pt18a ? l24t_a0 b20 1 (tc) 5 io pt17d ptck0c l25c_a0 b19 1 (tc) 5 io pt17c ptck0t l25t_a0 a20 1 (tc) 5 io pt17b ? l26c_a0 a19 1 (tc) 5 io pt17a ? l26t_a0 a18 1 (tc) 5 io pt16d vref_1_05 l27c_a0 b18 1 (tc) 5 io pt16c ? l27t_a0 y21 ?? vss vss ?? c17 1 (tc) 5 io pt16b ? l28c_d0 d16 1 (tc) 5 io pt16a ? l28t_d0 a17 1 (tc) 6 io pt15d ? l29c_d0 b16 1 (tc) 6 io pt15c ? l29t_d0 e15 1 (tc) 6 io pt15b ? l30c_a0 e14 1 (tc) 6 io pt15a ? l30t_a0 a16 1 (tc) 6 io pt14d ? l31c_a0 a15 1 (tc) 6 io pt14c vref_1_06 l31t_a0 y22 ?? vss vss ?? d14 1 (tc) 6 io pt14b ?? c16 0 (tl) 1 io pt13d mpi_rtry_n l1c_a0 c15 0 (tl) 1 io pt13c mpi_ack_n l1t_a0 d7 0 (tl) ? v dd io0 v dd io0 ?? c14 0 (tl) 1 io pt13b ? l2c_a0 b14 0 (tl) 1 io pt13a vref_0_01 l2t_a0 a14 0 (tl) 1 io pt12d m0 l3c_a0 a13 0 (tl) 1 io pt12c m1 l3t_a0 aa20 ?? vss vss ?? e12 0 (tl) 2 io pt12b mpi_clk l4c_a0 e13 0 (tl) 2 io pt12a a21/mpi_burst_n l4t_a0 c13 0 (tl) 2 io pt11d m2 l5c_a0 c12 0 (tl) 2 io pt11c m3 l5t_a0 b12 0 (tl) 2 io pt11b vref_0_02 l6c_a0 a12 0 (tl) 2 io pt11a mpi_tea_n l6t_a0
84 agere systems inc. preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel pin information (continued) table 27. ort82g5 680-pin pbgam pinout (continued) bm680 v dd io bank vref group i/o pin description additional function bm680 pair d12 0 (tl) 3 io pt10d ? l7c_d0 c11 0 (tl) 3 io pt10c ? l7t_d0 b11 0 (tl) 3 io pt10b ?? a11 0 (tl) 3 io pt9d vref_0_03 l8c_a0 a10 0 (tl) 3 io pt9c ? l8t_a0 aa21 ?? vss vss ?? b10 0 (tl) 3 io pt9b ?? e11 0 (tl) 3 io pt8d d0 l9c_d0 d10 0 (tl) 3 io pt8c tms l9t_d0 c10 0 (tl) 3 io pt8b ?? a9 0 (tl) 4 io pt7d a20/mpi_bdip_n l10c_a0 b9 0 (tl) 4 io pt7c a19/mpi_tsz1 l10t_a0 aa22 ?? vss vss ?? e10 0 (tl) 4 io pt7b ?? a8 0 (tl) 4 io pt6d a18/mpi_tsz0 l11c_a0 b8 0 (tl) 4 io pt6c d3 l11t_a0 d9 0 (tl) 4 io pt6b vref_0_04 l12c_d0 c8 0 (tl) 4 io pt6a ? l12t_d0 e9 0 (tl) 5 io pt5d d1 l13c_d0 d8 0 (tl) 5 io pt5c d2 l13t_d0 ab13 ?? vss vss ?? a7 0 (tl) 5 io pt5b ? l14c_a0 a6 0 (tl) 5 io pt5a vref_0_05 l14t_a0 c7 0 (tl) 5 io pt4d tdi l15c_d0 b6 0 (tl) 5 io pt4c tck l15t_d0 e8 0 (tl) 5 io pt4b ? l16c_a0 e7 0 (tl) 5 io pt4a ? l16t_a0 a5 0 (tl) 6 io pt3d ? l17c_a0 b5 0 (tl) 6 io pt3c vref_0_06 l17t_a0 ab14 ?? vss vss ?? c6 0 (tl) 6 io pt3b ? l18c_a0 d6 0 (tl) 6 io pt3a ? l18t_a0 c4 0 (tl) 6 io pt2d pll_ck1c/ppll l19c_a0 b4 0 (tl) 6 io pt2c pll_ck1t/ppll l19t_a0 a4 0 (tl) 6 io pt2b ? l20c_a0 a3 0 (tl) 6 io pt2a ? l20t_a0 d5 ?? o pcfg_mpi_irq cfg_irq_n/mpi_irq_n ? e6 ?? io pcclk cclk ? d4 ?? io pdone done ? e5 ?? v dd 33 v dd 33 ?? ab15 ?? vss vss ?? al33 ?? v dd 15 v dd 15 ??
agere systems inc. 85 preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel pin information (continued) table 27. ort82g5 680-pin pbgam pinout (continued) bm680 v dd io bank vref group i/o pin description additional function bm680 pair al34 ?? v dd 15 v dd 15 ?? am34 ?? v dd 15 v dd 15 ?? an34 ?? v dd 15 v dd 15 ?? b34 ?? v dd 15 v dd 15 ?? c33 ?? v dd 15 v dd 15 ?? c34 ?? v dd 15 v dd 15 ?? d33 ?? v dd 15 v dd 15 ?? d34 ?? v dd 15 v dd 15 ?? e32 ?? v dd 15 v dd 15 ?? e33 ?? v dd 15 v dd 15 ?? f32 ?? v dd 15 v dd 15 ?? f34 ?? v dd 15 v dd 15 ?? n16 ?? v dd 15 v dd 15 ?? n17 ?? v dd 15 v dd 15 ?? n18 ?? v dd 15 v dd 15 ?? n19 ?? v dd 15 v dd 15 ?? p16 ?? v dd 15 v dd 15 ?? p17 ?? v dd 15 v dd 15 ?? p18 ?? v dd 15 v dd 15 ?? p19 ?? v dd 15 v dd 15 ?? r16 ?? v dd 15 v dd 15 ?? r17 ?? v dd 15 v dd 15 ?? r18 ?? v dd 15 v dd 15 ?? r19 ?? v dd 15 v dd 15 ?? t13 ?? v dd 15 v dd 15 ?? t14 ?? v dd 15 v dd 15 ?? t15 ?? v dd 15 v dd 15 ?? t20 ?? v dd 15 v dd 15 ?? t21 ?? v dd 15 v dd 15 ?? t22 ?? v dd 15 v dd 15 ?? u13 ?? v dd 15 v dd 15 ?? u14 ?? v dd 15 v dd 15 ?? u15 ?? v dd 15 v dd 15 ?? u20 ?? v dd 15 v dd 15 ?? u21 ?? v dd 15 v dd 15 ?? u22 ?? v dd 15 v dd 15 ?? v13 ?? v dd 15 v dd 15 ?? v14 ?? v dd 15 v dd 15 ?? v15 ?? v dd 15 v dd 15 ?? v20 ?? v dd 15 v dd 15 ?? v21 ?? v dd 15 v dd 15 ?? v22 ?? v dd 15 v dd 15 ??
86 agere systems inc. preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel pin information (continued) table 27. ort82g5 680-pin pbgam pinout (continued) bm680 v dd io bank vref group i/o pin description additional function bm680 pair w13 ?? v dd 15 v dd 15 ?? w14 ?? v dd 15 v dd 15 ?? w15 ?? v dd 15 v dd 15 ?? w20 ?? v dd 15 v dd 15 ?? w21 ?? v dd 15 v dd 15 ?? w22 ?? v dd 15 v dd 15 ?? y16 ?? v dd 15 v dd 15 ?? y17 ?? v dd 15 v dd 15 ?? y18 ?? v dd 15 v dd 15 ?? y19 ?? v dd 15 v dd 15 ?? t32 ?? nc nc ?? w32 ?? nc nc ??
agere systems inc. 87 preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel package thermal characteristics summary there are three thermal parameters that are in com- mon use: ja , jc, and jc. it should be noted that all the parameters are affected, to varying degrees, by package design (including paddle size) and choice of materials, the amount of copper in the test board or system board, and system airflow. ja this is the thermal resistance from junction to ambient (theta-ja, r-theta, etc.): where t j is the junction temperature, t a, is the ambient air temperature, and q is the chip power. experimentally, ja is determined when a special ther- mal test die is assembled into the package of interest, and the part is mounted on the thermal test board. the diodes on the test chip are separately calibrated in an oven. the package/board is placed either in a jedec natural convection box or in the wind tunnel, the latter for forced convection measurements. a controlled amount of power (q) is dissipated in the test chip ? s heater resistor, the chip ? s temperature (t j ) is deter- mined by the forward drop on the diodes, and the ambi- ent temperature (t a ) is noted. note that ja is expressed in units of c/w. jc this jedec designated parameter correlates the junc- tion temperature to the case temperature. it is generally used to infer the junction temperature while the device is operating in the system. it is not considered a true thermal resistance and it is defined by: where t c is the case temperature at top dead center, t j is the junction temperature, and q is the chip power. during the ja measurements described above, besides the other parameters measured, an additional temperature reading, t c , is made with a thermocouple attached at top-dead-center of the case. jc is also expressed in units of c/w. jc this is the thermal resistance from junction to case. it is most often used when attaching a heat sink to the top of the package. it is defined by: the parameters in this equation have been defined above. however, the measurements are performed with the case of the part pressed against a water-cooled heat sink to draw most of the heat generated by the chip out the top of the package. it is this difference in the measurement process that differentiates jc from jc. jc is a true thermal resistance and is expressed in units of c/w. jb this is the thermal resistance from junction to board ( jl). it is defined by: where t b is the temperature of the board adjacent to a lead measured with a thermocouple. the other param- eters on the right-hand side have been defined above. this is considered a true thermal resistance, and the measurement is made with a water-cooled heat sink pressed against the board to draw most of the heat out of the leads. note that jb is expressed in units of c/w and that this parameter and the way it is mea- sured are still in jedec committee. fpsc maximum junction temperature once the power dissipated by the fpsc has been determined (see the estimating power dissipation sec- tion), the maximum junction temperature of the fpsc can be found. this is needed to determine if speed der- ating of the device from the 85 c junction temperature used in all of the delay tables is needed. using the maximum ambient temperature, t amax , and the power dissipated by the device, q (expressed in c), the max- imum junction temperature is approximated by: t jmax = t amax + (q ja) ta b l e 2 8 lists the thermal characteristics for all pack- ages used with the orca ort82g5 series of fpscs. ja t j t a ? q ------------------- - = jc t j t c ? q -------------------- = jc t j t c ? q -------------------- = jb t j t b ? q ------------------- - =
88 agere systems inc. preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel package thermal characteristics table 28 . orca ort82g5 plastic package thermal guidelines note: the 680-pin pbgam package for the ort82g5 includes a heat spreader. package coplanarity the coplanarity limits of the agere packages are as follows: pbgam: 8.0 mils package parasitics the electrical performance of an ic package, such as signal quality and noise sensitivity, is directly affected by the package parasitics. table 29 lists eight parasitics associated with the orca packages. these parasitics represent the contributions of all components of a package, which include the bond wires, all internal package routing, and the external leads. four inductances in nh are listed: l sw and l sl, the self-inductance of the lead; and l mw and l ml , the mutual inductance to the nearest neighbor lead. these parameters are important in determining ground bounce noise and inductive crosstalk noise. three capacitances in pf are listed: c m , the mutual capacitance of the lead to the near- est neighbor lead; and c 1 and c 2 , the total capacitance of the lead to all other leads (all other leads are assumed to be grounded). these parameters are important in determining capacitive crosstalk and the capacitive loading effect of the lead. resistance values are in m ?. the parasitic values in table 29 are for the circuit model of bond wire and package lead parasitics. if the mutual capacitance value is not used in the designer ? s model, then the value listed as mutual capacitance should be added to each of the c 1 and c 2 capacitors. table 29. orca ort82g5 package parasitics 5-3862(c)r2 figure 21. package parasitics package ja ( c/w) t = 85 c max t j = 125 c max 0 fpm (w) 0 fpm 200 fpm 500 fpm 680-pin pbgam 9.8 tbd tbd 4.1 package type l sw l mw r w c 1 c 2 c m l sl l ml 680-pin pbgam 3.8 1.3 250 1.0 1.0 0.3 2.8 ? 50.5 ? 1 pad n l sw r w board pad c m c 1 l sw r w l sl l mw c 2 c 1 l ml c 2 l sl pad n + 1
agere systems inc. 89 preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel package outline diagrams terms and definitions basic size (bsc): the basic size of a dimension is the size from which the limits for that dimension are derived by the application of the allowance and the tolerance. design size: the design size of a dimension is the actual size of the design, including an allowance for fit and tol- erance. typical (typ): when specified after a dimension, this indicates the repeated design size if a tolerance is specified or repeated basic size if a tolerance is not specified. reference (ref): the reference dimension is an untoleranced dimension used for informational purposes only. it is a repeated dimension or one that can be derived from other values in the drawing. minimum (min) or maximum (max): indicates the minimum or maximum allowable size of a dimension.
90 agere systems inc. preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel package outline diagrams (continued) 680-pin pbgam dimensions are in millimeters. 5-4406(f) seating plane solder ball 0.50 0.10 0.25 35.00 t d h al f k b p m l j ah r c e y n u an g ad v am aj ag ae ac aa w ap ak af ab a 19 30 26 28 24 32 22 20 18 4 6 8 10121416 2 34 52325 731 29 15 21 327 11 17 913 1 33 33 spaces @ 1.00 = 33.00 33 spaces a1 ball 0.64 0.15 a1 ball @ 1.00 = 33.00 corner 30.00 1.170 + 0.70 ? 0.00 35.00 30.00 + 0.70 ? 0.00 identifier zone 2.51 max 0.61 0.06
agere systems inc. 91 preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel hardware ordering information 5-6435(f) table 30. device type options table 31. temperature options table 32. package type options table 33 . orca fpsc package matrix (speed grades) software ordering information implementing a design in an ort82g5 requires the orca foundry development system and an ort82g5 fpsc design kit. for ordering information, please visit: http://www.agere.com/micro/netcom/ipkits/ort82g5/ device parameter value ort82g5 voltage 1.5 v core. 3.3 v/2.5 v i/o. package 680-pin pbgam. symbol description temperature (blank) industrial ? 40 c to +85 c symbol description bm plastic ball grid array, multilayer device package 680-pin pbgam bm680 ort82g5 ? 1, ? 2, -3 device type package type ort82g5 bm number of pins temperature range 680 -2 speed grade
agere systems inc. reserves the right to make changes to the product(s) or information contained herein without notice. no liab ility is assumed as a result of their use or application. orca is a registered trademark of agere systems inc. foundry is a trademark of xilinx, inc. copyright ? 2001 agere systems inc. all rights reserved printed in u.s.a. july 2001 ds01-218ncip for additional information, contact your agere systems account manager or the following: internet: http://www.agere.com or for fpgas/fpscs http://www.agere.com/orca e-mail: docmaster@agere.com n. america: agere systems inc., 555 union boulevard, room 30l-15p-ba, allentown, pa 18109-3286 1-800-372-2447 , fax 610-712-4106 (in canada: 1-800-553-2448 , fax 610-712-4106) asia pacific: agere systems singapore pte. ltd., 77 science park drive, #03-18 cintech iii, singapore 118256 tel. (65) 778 8833 , fax (65) 777 7495 china: agere systems (shanghai) co., ltd., 33/f jin mao tower, 88 century boulevard pudong, shanghai 200121 prc tel. (86) 21 50471212 , fax (86) 21 50472266 japan: agere systems japan ltd., 7-18, higashi-gotanda 2-chome, shinagawa-ku, tokyo 141, japan tel. (81) 3 5421 1600 , fax (81) 3 5421 1700 europe: data requests: dataline: tel. (44) 7000 582 368 , fax (44) 1189 328 148 technical inquiries: germany: (49) 89 95086 0 (munich), united kingdom: (44) 1344 865 900 (ascot), france: (33) 1 40 83 68 00 (paris), sweden: (46) 8 594 607 00 (stockholm), finland: (358) 9 3507670 (helsinki), italy: (39) 02 6608131 (milan), spain: (34) 1 807 1441 (madrid) preliminary data sheet july 2001 1.0-1.25/2.0-2.5/3.125 gbits/s backplane interface orca ort82g5 fpsc eight-channel infiniband is a trademark of infiniband trade association. ieee is a registered trademark of the institute of electrical and electronics engineers, inc. pa l is a trademark of advanced micro devices, inc. powerpc is a registered trademark of international business machines, inc. amba is a trademark, and arm is a registered trademark of advanced risc machines limited. synopsys smart model is a registered trademark of synopsys, inc. motorola is a registered trademark of motorola, inc. firewire is a registered trademark of apple computer, inc.

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